sh: Split out cache status bits per-CPU family.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

diff --git a/include/asm-sh/cache.h b/include/asm-sh/cache.h
index 01e5cf51ba9b38012469e7ceb0b78ab222e42fe5..083419f47c65a060a6d7ba20ab50954afa55f09d 100644 (file)
--- a/include/asm-sh/cache.h
+++ b/include/asm-sh/cache.h
@@ -12,11 +12,6 @@
 #include <linux/init.h>
 #include <asm/cpu/cache.h>
 
-#define SH_CACHE_VALID         1
-#define SH_CACHE_UPDATED       2
-#define SH_CACHE_COMBINED      4
-#define SH_CACHE_ASSOC         8
-
 #define L1_CACHE_BYTES         (1 << L1_CACHE_SHIFT)
 
 #define __read_mostly __attribute__((__section__(".data.read_mostly")))

diff --git a/include/asm-sh/cpu-sh2/cache.h b/include/asm-sh/cpu-sh2/cache.h
index f02ba7a672b227c5fb8acfb14a5a5f945f7a5224..66388ce16c30da11a9d8a3a4b9b1a1d66a08bbbb 100644 (file)
--- a/include/asm-sh/cpu-sh2/cache.h
+++ b/include/asm-sh/cpu-sh2/cache.h
@@ -12,6 +12,11 @@
 
 #define L1_CACHE_SHIFT 4
 
+#define SH_CACHE_VALID         1
+#define SH_CACHE_UPDATED       2
+#define SH_CACHE_COMBINED      4
+#define SH_CACHE_ASSOC         8
+
 #if defined(CONFIG_CPU_SUBTYPE_SH7619)
 #define CCR1           0xffffffec
 #define CCR            CCR1

diff --git a/include/asm-sh/cpu-sh2a/cache.h b/include/asm-sh/cpu-sh2a/cache.h
index 3e4b9e4809829ced0a5a9af35491c631db7a814e..d88774169b588dc82360681d3aef901985d88249 100644 (file)
--- a/include/asm-sh/cpu-sh2a/cache.h
+++ b/include/asm-sh/cpu-sh2a/cache.h
@@ -12,6 +12,11 @@
 
 #define L1_CACHE_SHIFT 4
 
+#define SH_CACHE_VALID         1
+#define SH_CACHE_UPDATED       2
+#define SH_CACHE_COMBINED      4
+#define SH_CACHE_ASSOC         8
+
 #define CCR1           0xfffc1000
 #define CCR2           0xfffc1004
 

diff --git a/include/asm-sh/cpu-sh3/cache.h b/include/asm-sh/cpu-sh3/cache.h
index 255016fc91f09b7eecd1e725379881e65b4e9571..77dd45d8241490a0bf3ced9fd0107dff21afcc75 100644 (file)
--- a/include/asm-sh/cpu-sh3/cache.h
+++ b/include/asm-sh/cpu-sh3/cache.h
@@ -12,6 +12,11 @@
 
 #define L1_CACHE_SHIFT 4
 
+#define SH_CACHE_VALID         1
+#define SH_CACHE_UPDATED       2
+#define SH_CACHE_COMBINED      4
+#define SH_CACHE_ASSOC         8
+
 #define CCR            0xffffffec      /* Address of Cache Control Register */
 
 #define CCR_CACHE_CE   0x01    /* Cache Enable */

diff --git a/include/asm-sh/cpu-sh4/cache.h b/include/asm-sh/cpu-sh4/cache.h
index f92b20a0983d7e6001cb5e8a548a09e8966fbddb..1c61ebf5c8e3bfb0a6d025c5d8ca4a338b13027b 100644 (file)
--- a/include/asm-sh/cpu-sh4/cache.h
+++ b/include/asm-sh/cpu-sh4/cache.h
@@ -12,6 +12,11 @@
 
 #define L1_CACHE_SHIFT 5
 
+#define SH_CACHE_VALID         1
+#define SH_CACHE_UPDATED       2
+#define SH_CACHE_COMBINED      4
+#define SH_CACHE_ASSOC         8
+
 #define CCR            0xff00001c      /* Address of Cache Control Register */
 #define CCR_CACHE_OCE  0x0001  /* Operand Cache Enable */
 #define CCR_CACHE_WT   0x0002  /* Write-Through (for P0,U0,P3) (else writeback)*/