clk: mediatek: fhctl: Add support for older fhctl register layout

The Frequency Hopping Controller (FHCTL) seems to have different
versions, as it has a slightly different register layout on some
older SoCs like MT6795, MT8173, MT8183 (and others).

This driver is indeed compatible with at least some of those older
IP revisions, so all we need to do is to add a way to select the
right register layout at registration time.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230206100105.861720-2-angelogioacchino.delregno@collabora.com
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/mediatek/clk-fhctl.c b/drivers/clk/mediatek/clk-fhctl.c
index 4f271acef5fe83e809e4eda0d92e917e165a385f..45e4842cbf04eb3aae67d3e460807c0edb3b2900 100644 (file)
--- a/drivers/clk/mediatek/clk-fhctl.c
+++ b/drivers/clk/mediatek/clk-fhctl.c
@@ -14,7 +14,20 @@
 #define PERCENT_TO_DDSLMT(dds, percent_m10) \
        ((((dds) * (percent_m10)) >> 5) / 100)
 
-static const struct fhctl_offset fhctl_offset = {
+const struct fhctl_offset fhctl_offset_v1 = {
+       .offset_hp_en = 0x0,
+       .offset_clk_con = 0x4,
+       .offset_rst_con = 0x8,
+       .offset_slope0 = 0xc,
+       .offset_slope1 = 0x10,
+       .offset_cfg = 0x0,
+       .offset_updnlmt = 0x4,
+       .offset_dds = 0x8,
+       .offset_dvfs = 0xc,
+       .offset_mon = 0x10,
+};
+
+const struct fhctl_offset fhctl_offset_v2 = {
        .offset_hp_en = 0x0,
        .offset_clk_con = 0x8,
        .offset_rst_con = 0xc,
@@ -27,9 +40,16 @@ static const struct fhctl_offset fhctl_offset = {
        .offset_mon = 0x10,
 };
 
-const struct fhctl_offset *fhctl_get_offset_table(void)
+const struct fhctl_offset *fhctl_get_offset_table(enum fhctl_variant v)
 {
-       return &fhctl_offset;
+       switch (v) {
+       case FHCTL_PLLFH_V1:
+               return &fhctl_offset_v1;
+       case FHCTL_PLLFH_V2:
+               return &fhctl_offset_v2;
+       default:
+               return ERR_PTR(-EINVAL);
+       };
 }
 
 static void dump_hw(struct mtk_clk_pll *pll, struct fh_pll_regs *regs,

diff --git a/drivers/clk/mediatek/clk-fhctl.h b/drivers/clk/mediatek/clk-fhctl.h
index 51275febf08667f1b550d1373f905c9ad69f4ed2..bfa6d281a3ee3f830a31b32c81a74f9ea304c33b 100644 (file)
--- a/drivers/clk/mediatek/clk-fhctl.h
+++ b/drivers/clk/mediatek/clk-fhctl.h
@@ -7,6 +7,13 @@
 #ifndef __CLK_FHCTL_H
 #define __CLK_FHCTL_H
 
+#include "clk-pllfh.h"
+
+enum fhctl_variant {
+       FHCTL_PLLFH_V1,
+       FHCTL_PLLFH_V2,
+};
+
 struct fhctl_offset {
        u32 offset_hp_en;
        u32 offset_clk_con;
@@ -19,7 +26,7 @@ struct fhctl_offset {
        u32 offset_dvfs;
        u32 offset_mon;
 };
-const struct fhctl_offset *fhctl_get_offset_table(void);
+const struct fhctl_offset *fhctl_get_offset_table(enum fhctl_variant v);
 const struct fh_operation *fhctl_get_ops(void);
 void fhctl_hw_init(struct mtk_fh *fh);
 

diff --git a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c
index 1d673c6278a9dc354ae850eed32e2c44cf91fe5c..9fded5020ca43e0a1f41db1e4e070253531b5d89 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c
@@ -7,6 +7,7 @@
 #include <linux/platform_device.h>
 #include <dt-bindings/clock/mt8186-clk.h>
 
+#include "clk-fhctl.h"
 #include "clk-mtk.h"
 #include "clk-pll.h"
 #include "clk-pllfh.h"
@@ -98,6 +99,7 @@ enum fh_pll_id {
                .data = {                                               \
                        .pll_id = _pllid,                               \
                        .fh_id = _fhid,                                 \
+                       .fh_ver = FHCTL_PLLFH_V2,                       \
                        .fhx_offset = _offset,                          \
                        .dds_mask = GENMASK(21, 0),                     \
                        .slope0_value = 0x6003c97,                      \

diff --git a/drivers/clk/mediatek/clk-pllfh.c b/drivers/clk/mediatek/clk-pllfh.c
index f48780bec5077ae27aad22bd59a654e94734bdcb..b9297726f5a038bd57da5cc7553910534bf71c5e 100644 (file)
--- a/drivers/clk/mediatek/clk-pllfh.c
+++ b/drivers/clk/mediatek/clk-pllfh.c
@@ -104,14 +104,16 @@ void fhctl_parse_dt(const u8 *compatible_node, struct mtk_pllfh_data *pllfhs,
        }
 }
 
-static void pllfh_init(struct mtk_fh *fh, struct mtk_pllfh_data *pllfh_data)
+static int pllfh_init(struct mtk_fh *fh, struct mtk_pllfh_data *pllfh_data)
 {
        struct fh_pll_regs *regs = &fh->regs;
        const struct fhctl_offset *offset;
        void __iomem *base = pllfh_data->state.base;
        void __iomem *fhx_base = base + pllfh_data->data.fhx_offset;
 
-       offset = fhctl_get_offset_table();
+       offset = fhctl_get_offset_table(pllfh_data->data.fh_ver);
+       if (IS_ERR(offset))
+               return PTR_ERR(offset);
 
        regs->reg_hp_en = base + offset->offset_hp_en;
        regs->reg_clk_con = base + offset->offset_clk_con;
@@ -129,6 +131,8 @@ static void pllfh_init(struct mtk_fh *fh, struct mtk_pllfh_data *pllfh_data)
        fh->lock = &pllfh_lock;
 
        fh->ops = fhctl_get_ops();
+
+       return 0;
 }
 
 static bool fhctl_is_supported_and_enabled(const struct mtk_pllfh_data *pllfh)
@@ -142,20 +146,29 @@ mtk_clk_register_pllfh(const struct mtk_pll_data *pll_data,
 {
        struct clk_hw *hw;
        struct mtk_fh *fh;
+       int ret;
 
        fh = kzalloc(sizeof(*fh), GFP_KERNEL);
        if (!fh)
                return ERR_PTR(-ENOMEM);
 
-       pllfh_init(fh, pllfh_data);
+       ret = pllfh_init(fh, pllfh_data);
+       if (ret) {
+               hw = ERR_PTR(ret);
+               goto out;
+       }
 
        hw = mtk_clk_register_pll_ops(&fh->clk_pll, pll_data, base,
                                      &mtk_pllfh_ops);
 
+       if (IS_ERR(hw))
+               goto out;
+
+       fhctl_hw_init(fh);
+
+out:
        if (IS_ERR(hw))
                kfree(fh);
-       else
-               fhctl_hw_init(fh);
 
        return hw;
 }

diff --git a/drivers/clk/mediatek/clk-pllfh.h b/drivers/clk/mediatek/clk-pllfh.h
index c0a6e1537034f8d3827d894288cf399109d39f87..5f419c2ec01f988ede4e40289c6e5d5f8070ad14 100644 (file)
--- a/drivers/clk/mediatek/clk-pllfh.h
+++ b/drivers/clk/mediatek/clk-pllfh.h
@@ -18,6 +18,7 @@ struct fh_pll_state {
 struct fh_pll_data {
        int pll_id;
        int fh_id;
+       int fh_ver;
        u32 fhx_offset;
        u32 dds_mask;
        u32 slope0_value;