* Switch to DATA IN phase but wait until initial data xfer is
* complete before raising the command completion interrupt
*/
- s->data_in_ready = false;
+ s->data_ready = false;
esp_set_phase(s, STAT_DI);
} else {
esp_set_phase(s, STAT_DO);
s->async_len = len;
s->async_buf = scsi_req_get_buf(req);
- if (!to_device && !s->data_in_ready) {
+ if (!to_device && !s->data_ready) {
/*
* Initial incoming data xfer is complete so raise command
* completion interrupt
*/
- s->data_in_ready = true;
+ s->data_ready = true;
s->rregs[ESP_RINTR] |= INTR_BS;
esp_raise_irq(s);
}
VMSTATE_UINT32_TEST(mig_cmdlen, ESPState, esp_is_before_version_5),
VMSTATE_UINT32(do_cmd, ESPState),
VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5),
- VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5),
+ VMSTATE_BOOL_TEST(data_ready, ESPState, esp_is_version_5),
VMSTATE_UINT8_TEST(cmdfifo_cdb_offset, ESPState, esp_is_version_5),
VMSTATE_FIFO8_TEST(fifo, ESPState, esp_is_version_5),
VMSTATE_FIFO8_TEST(cmdfifo, ESPState, esp_is_version_5),