RDMA/hfi1: Use RMW accessors for changing LNKCTL2

Convert open coded RMW accesses for LNKCTL2 to use
pcie_capability_clear_and_set_word() which makes its easier to
understand what the code tries to do.

In addition, this futureproofs the code. LNKCTL2 is not really owned by
any driver because it is a collection of control bits that PCI core
might need to touch. RMW accessors already have support for proper
locking for a selected set of registers to avoid losing concurrent
updates (LNKCTL2 is not yet among the registers that need protection
but likely will be in the future).

Suggested-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Link: https://lore.kernel.org/r/20240503133640.15899-1-ilpo.jarvinen@linux.intel.com
Reviewed-by: Dean Luick <dean.luick@cornelisnetworks.com>
Signed-off-by: Leon Romanovsky <leon@kernel.org>

diff --git a/drivers/infiniband/hw/hfi1/pcie.c b/drivers/infiniband/hw/hfi1/pcie.c
index 119ec2f1382bf83d4f4ac16b5e899d5125e461a5..7133964749f80a0c3865c2e573fd4bf809c7b073 100644 (file)
--- a/drivers/infiniband/hw/hfi1/pcie.c
+++ b/drivers/infiniband/hw/hfi1/pcie.c
@@ -1207,14 +1207,11 @@ retry:
                    (u32)lnkctl2);
        /* only write to parent if target is not as high as ours */
        if ((lnkctl2 & PCI_EXP_LNKCTL2_TLS) < target_vector) {
-               lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS;
-               lnkctl2 |= target_vector;
-               dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__,
-                           (u32)lnkctl2);
-               ret = pcie_capability_write_word(parent,
-                                                PCI_EXP_LNKCTL2, lnkctl2);
+               ret = pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL2,
+                                                        PCI_EXP_LNKCTL2_TLS,
+                                                        target_vector);
                if (ret) {
-                       dd_dev_err(dd, "Unable to write to PCI config\n");
+                       dd_dev_err(dd, "Unable to change parent PCI target speed\n");
                        return_error = 1;
                        goto done;
                }
@@ -1223,22 +1220,11 @@ retry:
        }
 
        dd_dev_info(dd, "%s: setting target link speed\n", __func__);
-       ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL2, &lnkctl2);
+       ret = pcie_capability_clear_and_set_word(dd->pcidev, PCI_EXP_LNKCTL2,
+                                                PCI_EXP_LNKCTL2_TLS,
+                                                target_vector);
        if (ret) {
-               dd_dev_err(dd, "Unable to read from PCI config\n");
-               return_error = 1;
-               goto done;
-       }
-
-       dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__,
-                   (u32)lnkctl2);
-       lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS;
-       lnkctl2 |= target_vector;
-       dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__,
-                   (u32)lnkctl2);
-       ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL2, lnkctl2);
-       if (ret) {
-               dd_dev_err(dd, "Unable to write to PCI config\n");
+               dd_dev_err(dd, "Unable to change device PCI target speed\n");
                return_error = 1;
                goto done;
        }