net: ethernet: am65-cpsw: Move register definitions to header file
authorRoger Quadros <rogerq@kernel.org>
Tue, 19 Dec 2023 10:58:02 +0000 (12:58 +0200)
committerDavid S. Miller <davem@davemloft.net>
Sat, 23 Dec 2023 01:01:19 +0000 (01:01 +0000)
Move register definitions to header file. No functional change.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/ti/am65-cpsw-qos.c
drivers/net/ethernet/ti/am65-cpsw-qos.h

index 862a98211caa9dc482dbddbc6bcfe7685312b59c..9f0a05e763d1d45921cc2ae524fd08fbc9fbb4d3 100644 (file)
 #include "am65-cpts.h"
 #include "cpsw_ale.h"
 
-#define AM65_CPSW_REG_CTL                      0x004
-#define AM65_CPSW_PN_REG_CTL                   0x004
-#define AM65_CPSW_PN_REG_FIFO_STATUS           0x050
-#define AM65_CPSW_PN_REG_EST_CTL               0x060
-#define AM65_CPSW_PN_REG_PRI_CIR(pri)          (0x140 + 4 * (pri))
-
-/* AM65_CPSW_REG_CTL register fields */
-#define AM65_CPSW_CTL_EST_EN                   BIT(18)
-
-/* AM65_CPSW_PN_REG_CTL register fields */
-#define AM65_CPSW_PN_CTL_EST_PORT_EN           BIT(17)
-
-/* AM65_CPSW_PN_REG_EST_CTL register fields */
-#define AM65_CPSW_PN_EST_ONEBUF                        BIT(0)
-#define AM65_CPSW_PN_EST_BUFSEL                        BIT(1)
-#define AM65_CPSW_PN_EST_TS_EN                 BIT(2)
-#define AM65_CPSW_PN_EST_TS_FIRST              BIT(3)
-#define AM65_CPSW_PN_EST_ONEPRI                        BIT(4)
-#define AM65_CPSW_PN_EST_TS_PRI_MSK            GENMASK(7, 5)
-
-/* AM65_CPSW_PN_REG_FIFO_STATUS register fields */
-#define AM65_CPSW_PN_FST_TX_PRI_ACTIVE_MSK     GENMASK(7, 0)
-#define AM65_CPSW_PN_FST_TX_E_MAC_ALLOW_MSK    GENMASK(15, 8)
-#define AM65_CPSW_PN_FST_EST_CNT_ERR           BIT(16)
-#define AM65_CPSW_PN_FST_EST_ADD_ERR           BIT(17)
-#define AM65_CPSW_PN_FST_EST_BUFACT            BIT(18)
-
-/* EST FETCH COMMAND RAM */
-#define AM65_CPSW_FETCH_RAM_CMD_NUM            0x80
-#define AM65_CPSW_FETCH_CNT_MSK                        GENMASK(21, 8)
-#define AM65_CPSW_FETCH_CNT_MAX                        (AM65_CPSW_FETCH_CNT_MSK >> 8)
-#define AM65_CPSW_FETCH_CNT_OFFSET             8
-#define AM65_CPSW_FETCH_ALLOW_MSK              GENMASK(7, 0)
-#define AM65_CPSW_FETCH_ALLOW_MAX              AM65_CPSW_FETCH_ALLOW_MSK
-
 enum timer_act {
        TACT_PROG,              /* need program timer */
        TACT_NEED_STOP,         /* need stop first */
index be4987eb8c5152f481771f3071ed35bfec5bfe38..e3259f27baadbfc225cb4f1792ceed35b18b6712 100644 (file)
@@ -31,6 +31,41 @@ struct am65_cpsw_qos {
        struct am65_cpsw_ale_ratelimit ale_mc_ratelimit;
 };
 
+#define AM65_CPSW_REG_CTL                      0x004
+#define AM65_CPSW_PN_REG_CTL                   0x004
+#define AM65_CPSW_PN_REG_FIFO_STATUS           0x050
+#define AM65_CPSW_PN_REG_EST_CTL               0x060
+#define AM65_CPSW_PN_REG_PRI_CIR(pri)          (0x140 + 4 * (pri))
+
+/* AM65_CPSW_REG_CTL register fields */
+#define AM65_CPSW_CTL_EST_EN                   BIT(18)
+
+/* AM65_CPSW_PN_REG_CTL register fields */
+#define AM65_CPSW_PN_CTL_EST_PORT_EN           BIT(17)
+
+/* AM65_CPSW_PN_REG_EST_CTL register fields */
+#define AM65_CPSW_PN_EST_ONEBUF                        BIT(0)
+#define AM65_CPSW_PN_EST_BUFSEL                        BIT(1)
+#define AM65_CPSW_PN_EST_TS_EN                 BIT(2)
+#define AM65_CPSW_PN_EST_TS_FIRST              BIT(3)
+#define AM65_CPSW_PN_EST_ONEPRI                        BIT(4)
+#define AM65_CPSW_PN_EST_TS_PRI_MSK            GENMASK(7, 5)
+
+/* AM65_CPSW_PN_REG_FIFO_STATUS register fields */
+#define AM65_CPSW_PN_FST_TX_PRI_ACTIVE_MSK     GENMASK(7, 0)
+#define AM65_CPSW_PN_FST_TX_E_MAC_ALLOW_MSK    GENMASK(15, 8)
+#define AM65_CPSW_PN_FST_EST_CNT_ERR           BIT(16)
+#define AM65_CPSW_PN_FST_EST_ADD_ERR           BIT(17)
+#define AM65_CPSW_PN_FST_EST_BUFACT            BIT(18)
+
+/* EST FETCH COMMAND RAM */
+#define AM65_CPSW_FETCH_RAM_CMD_NUM            0x80
+#define AM65_CPSW_FETCH_CNT_MSK                        GENMASK(21, 8)
+#define AM65_CPSW_FETCH_CNT_MAX                        (AM65_CPSW_FETCH_CNT_MSK >> 8)
+#define AM65_CPSW_FETCH_CNT_OFFSET             8
+#define AM65_CPSW_FETCH_ALLOW_MSK              GENMASK(7, 0)
+#define AM65_CPSW_FETCH_ALLOW_MAX              AM65_CPSW_FETCH_ALLOW_MSK
+
 #if IS_ENABLED(CONFIG_TI_AM65_CPSW_QOS)
 int am65_cpsw_qos_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type,
                               void *type_data);