drm/i915/dsc: Refactor dsc gen checks

Use HAS_DSC(__i915) wrapper containing runtime info of has_dsc
member. Platforms supporting dsc has this flag enabled; no need of
DISPLAY_VER() check.

Also, simplified intel_dsc_source_support() based on above changes.

Suggested-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221110093312.13932-1-swati2.sharma@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index cf8a2f644baba158bcb907af10671c08adaf6331..1607c86af025af0431c81dd464536c7b3d28f8d7 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1013,7 +1013,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
         * Output bpp is stored in 6.4 format so right shift by 4 to get the
         * integer value since we support only integer values of bpp.
         */
-       if (DISPLAY_VER(dev_priv) >= 10 &&
+       if (HAS_DSC(dev_priv) &&
            drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
                /*
                 * TBD pass the connector BPC,
@@ -2926,7 +2926,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
        intel_dp_set_max_sink_lane_count(intel_dp);
 
        /* Read the eDP DSC DPCD registers */
-       if (DISPLAY_VER(dev_priv) >= 10)
+       if (HAS_DSC(dev_priv))
                intel_dp_get_dsc_sink_cap(intel_dp);
 
        /*
@@ -4711,7 +4711,7 @@ intel_dp_detect(struct drm_connector *connector,
        }
 
        /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
-       if (DISPLAY_VER(dev_priv) >= 11)
+       if (HAS_DSC(dev_priv))
                intel_dp_get_dsc_sink_cap(intel_dp);
 
        intel_dp_configure_mst(intel_dp);

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 9d3b77b41b5c1931c6dbf7b4c3c9b7ddf8a5e160..207b2a648d326097093975d6fc9199a123e55939 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -345,16 +345,13 @@ bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
        struct drm_i915_private *i915 = to_i915(crtc->base.dev);
        enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
-       if (!RUNTIME_INFO(i915)->has_dsc)
+       if (!HAS_DSC(i915))
                return false;
 
-       if (DISPLAY_VER(i915) >= 12)
-               return true;
-
-       if (DISPLAY_VER(i915) >= 11 && cpu_transcoder != TRANSCODER_A)
-               return true;
+       if (DISPLAY_VER(i915) == 11 && cpu_transcoder == TRANSCODER_A)
+               return false;
 
-       return false;
+       return true;
 }
 
 static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2f074d7e0d31d17744ee2c72013a05fcca2d1404..d2b9981d736ed1d3cbfa3e80259a2767e393369e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -469,6 +469,7 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
 #define INTEL_REVID(dev_priv)  (to_pci_dev((dev_priv)->drm.dev)->revision)
 
 #define HAS_DSB(dev_priv)      (INTEL_INFO(dev_priv)->display.has_dsb)
+#define HAS_DSC(__i915)                (RUNTIME_INFO(__i915)->has_dsc)
 
 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
 #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)