clk: qcom: gcc-msm8939: Add missing CSI2 related clocks

When adding in the indexes for this clock-controller we missed
GCC_CAMSS_CSI2_AHB_CLK, GCC_CAMSS_CSI2_CLK, GCC_CAMSS_CSI2PHY_CLK,
GCC_CAMSS_CSI2PIX_CLK and GCC_CAMSS_CSI2RDI_CLK.

Add them in now and rename ftbl_gcc_camss_csi0_1_clk
to account for csi2 also using it.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org>
Link: https://lore.kernel.org/r/20231029061948.505883-2-vincent.knecht@mailoo.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c
index b45f97c07eeb6ffd27caad22297490a19ecc153b..7b9a3e99b589206864a6eab2512be1a7dbf94311 100644 (file)
--- a/drivers/clk/qcom/gcc-msm8939.c
+++ b/drivers/clk/qcom/gcc-msm8939.c
@@ -696,7 +696,7 @@ static struct clk_rcg2 apss_ahb_clk_src = {
        },
 };
 
-static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
+static const struct freq_tbl ftbl_gcc_camss_csi0_1_2_clk[] = {
        F(100000000, P_GPLL0, 8, 0,     0),
        F(200000000, P_GPLL0, 4, 0,     0),
        { }
@@ -706,7 +706,7 @@ static struct clk_rcg2 csi0_clk_src = {
        .cmd_rcgr = 0x4e020,
        .hid_width = 5,
        .parent_map = gcc_xo_gpll0_map,
-       .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
+       .freq_tbl = ftbl_gcc_camss_csi0_1_2_clk,
        .clkr.hw.init = &(struct clk_init_data){
                .name = "csi0_clk_src",
                .parent_data = gcc_xo_gpll0_parent_data,
@@ -719,7 +719,7 @@ static struct clk_rcg2 csi1_clk_src = {
        .cmd_rcgr = 0x4f020,
        .hid_width = 5,
        .parent_map = gcc_xo_gpll0_map,
-       .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
+       .freq_tbl = ftbl_gcc_camss_csi0_1_2_clk,
        .clkr.hw.init = &(struct clk_init_data){
                .name = "csi1_clk_src",
                .parent_data = gcc_xo_gpll0_parent_data,
@@ -728,6 +728,19 @@ static struct clk_rcg2 csi1_clk_src = {
        },
 };
 
+static struct clk_rcg2 csi2_clk_src = {
+       .cmd_rcgr = 0x3c020,
+       .hid_width = 5,
+       .parent_map = gcc_xo_gpll0_map,
+       .freq_tbl = ftbl_gcc_camss_csi0_1_2_clk,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "csi2_clk_src",
+               .parent_data = gcc_xo_gpll0_parent_data,
+               .num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
+               .ops = &clk_rcg2_ops,
+       },
+};
+
 static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
        F(19200000, P_XO, 1, 0, 0),
        F(50000000, P_GPLL0, 16, 0, 0),
@@ -2385,6 +2398,91 @@ static struct clk_branch gcc_camss_csi1rdi_clk = {
        },
 };
 
+static struct clk_branch gcc_camss_csi2_ahb_clk = {
+       .halt_reg = 0x3c040,
+       .clkr = {
+               .enable_reg = 0x3c040,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_camss_csi2_ahb_clk",
+                       .parent_hws = (const struct clk_hw*[]){
+                               &camss_ahb_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_camss_csi2_clk = {
+       .halt_reg = 0x3c03c,
+       .clkr = {
+               .enable_reg = 0x3c03c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_camss_csi2_clk",
+                       .parent_hws = (const struct clk_hw*[]){
+                               &csi2_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_camss_csi2phy_clk = {
+       .halt_reg = 0x3c048,
+       .clkr = {
+               .enable_reg = 0x3c048,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_camss_csi2phy_clk",
+                       .parent_hws = (const struct clk_hw*[]){
+                               &csi2_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_camss_csi2pix_clk = {
+       .halt_reg = 0x3c058,
+       .clkr = {
+               .enable_reg = 0x3c058,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_camss_csi2pix_clk",
+                       .parent_hws = (const struct clk_hw*[]){
+                               &csi2_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch gcc_camss_csi2rdi_clk = {
+       .halt_reg = 0x3c050,
+       .clkr = {
+               .enable_reg = 0x3c050,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_camss_csi2rdi_clk",
+                       .parent_hws = (const struct clk_hw*[]){
+                               &csi2_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
 static struct clk_branch gcc_camss_csi_vfe0_clk = {
        .halt_reg = 0x58050,
        .clkr = {
@@ -3682,6 +3780,7 @@ static struct clk_regmap *gcc_msm8939_clocks[] = {
        [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
        [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
        [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
+       [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
        [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
        [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
        [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
@@ -3751,6 +3850,11 @@ static struct clk_regmap *gcc_msm8939_clocks[] = {
        [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
        [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
        [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
+       [GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr,
+       [GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr,
+       [GCC_CAMSS_CSI2PHY_CLK] = &gcc_camss_csi2phy_clk.clkr,
+       [GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr,
+       [GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr,
        [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
        [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
        [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,