clk: ingenic: Minor cosmetic fixups for X1000

Remove redundant -1 entries from the parents array and fix
a couple indentation / whitespace issues.

Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Link: https://lore.kernel.org/r/20221026194345.243007-7-aidanmacdonald.0x0@gmail.com
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c
index 95d5e3a44cee3ce71646eae8e952de4def1c614d..feb03eed4fe8c8f617ef98254a522d72d452ac17 100644 (file)
--- a/drivers/clk/ingenic/x1000-cgu.c
+++ b/drivers/clk/ingenic/x1000-cgu.c
@@ -216,7 +216,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
 
        [X1000_CLK_APLL] = {
                "apll", CGU_CLK_PLL,
-               .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+               .parents = { X1000_CLK_EXCLK },
                .pll = {
                        .reg = CGU_REG_APLL,
                        .rate_multiplier = 1,
@@ -239,7 +239,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
 
        [X1000_CLK_MPLL] = {
                "mpll", CGU_CLK_PLL,
-               .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+               .parents = { X1000_CLK_EXCLK },
                .pll = {
                        .reg = CGU_REG_MPLL,
                        .rate_multiplier = 1,
@@ -289,7 +289,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
                 * system; mark it critical.
                 */
                .flags = CLK_IS_CRITICAL,
-               .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
+               .parents = { X1000_CLK_CPUMUX },
                .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
                .gate = { CGU_REG_CLKGR, 30 },
        },
@@ -301,7 +301,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
                 * disabling it or any parent clocks will hang the system.
                 */
                .flags = CLK_IS_CRITICAL,
-               .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
+               .parents = { X1000_CLK_CPUMUX },
                .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
        },
 
@@ -320,13 +320,13 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
 
        [X1000_CLK_AHB2] = {
                "ahb2", CGU_CLK_DIV,
-               .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
+               .parents = { X1000_CLK_AHB2PMUX },
                .div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 },
        },
 
        [X1000_CLK_PCLK] = {
                "pclk", CGU_CLK_DIV | CGU_CLK_GATE,
-               .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
+               .parents = { X1000_CLK_AHB2PMUX },
                .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 },
                .gate = { CGU_REG_CLKGR, 28 },
        },
@@ -393,13 +393,13 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
 
        [X1000_CLK_MSCMUX] = {
                "msc_mux", CGU_CLK_MUX,
-               .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL},
+               .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL },
                .mux = { CGU_REG_MSC0CDR, 31, 1 },
        },
 
        [X1000_CLK_MSC0] = {
                "msc0", CGU_CLK_DIV | CGU_CLK_GATE,
-               .parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
+               .parents = { X1000_CLK_MSCMUX },
                .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 },
                .gate = { CGU_REG_CLKGR, 4 },
        },
@@ -413,8 +413,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
 
        [X1000_CLK_OTG] = {
                "otg", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
-               .parents = { X1000_CLK_EXCLK, -1,
-                                        X1000_CLK_APLL, X1000_CLK_MPLL },
+               .parents = { X1000_CLK_EXCLK, -1, X1000_CLK_APLL, X1000_CLK_MPLL },
                .mux = { CGU_REG_USBCDR, 30, 2 },
                .div = { CGU_REG_USBCDR, 0, 1, 8, 29, 28, 27 },
                .gate = { CGU_REG_CLKGR, 3 },
@@ -422,7 +421,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
 
        [X1000_CLK_SSIPLL] = {
                "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
-               .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 },
+               .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL },
                .mux = { CGU_REG_SSICDR, 31, 1 },
                .div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 },
        },
@@ -435,7 +434,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
 
        [X1000_CLK_SSIMUX] = {
                "ssi_mux", CGU_CLK_MUX,
-               .parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL_DIV2, -1, -1 },
+               .parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL_DIV2 },
                .mux = { CGU_REG_SSICDR, 30, 1 },
        },
 
@@ -456,37 +455,37 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
 
        [X1000_CLK_EMC] = {
                "emc", CGU_CLK_GATE,
-               .parents = { X1000_CLK_AHB2, -1, -1, -1 },
+               .parents = { X1000_CLK_AHB2 },
                .gate = { CGU_REG_CLKGR, 0 },
        },
 
        [X1000_CLK_EFUSE] = {
                "efuse", CGU_CLK_GATE,
-               .parents = { X1000_CLK_AHB2, -1, -1, -1 },
+               .parents = { X1000_CLK_AHB2 },
                .gate = { CGU_REG_CLKGR, 1 },
        },
 
        [X1000_CLK_SFC] = {
                "sfc", CGU_CLK_GATE,
-               .parents = { X1000_CLK_SSIPLL, -1, -1, -1 },
+               .parents = { X1000_CLK_SSIPLL },
                .gate = { CGU_REG_CLKGR, 2 },
        },
 
        [X1000_CLK_I2C0] = {
                "i2c0", CGU_CLK_GATE,
-               .parents = { X1000_CLK_PCLK, -1, -1, -1 },
+               .parents = { X1000_CLK_PCLK },
                .gate = { CGU_REG_CLKGR, 7 },
        },
 
        [X1000_CLK_I2C1] = {
                "i2c1", CGU_CLK_GATE,
-               .parents = { X1000_CLK_PCLK, -1, -1, -1 },
+               .parents = { X1000_CLK_PCLK },
                .gate = { CGU_REG_CLKGR, 8 },
        },
 
        [X1000_CLK_I2C2] = {
                "i2c2", CGU_CLK_GATE,
-               .parents = { X1000_CLK_PCLK, -1, -1, -1 },
+               .parents = { X1000_CLK_PCLK },
                .gate = { CGU_REG_CLKGR, 9 },
        },
 
@@ -498,43 +497,43 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
 
        [X1000_CLK_UART0] = {
                "uart0", CGU_CLK_GATE,
-               .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+               .parents = { X1000_CLK_EXCLK },
                .gate = { CGU_REG_CLKGR, 14 },
        },
 
        [X1000_CLK_UART1] = {
                "uart1", CGU_CLK_GATE,
-               .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+               .parents = { X1000_CLK_EXCLK},
                .gate = { CGU_REG_CLKGR, 15 },
        },
 
        [X1000_CLK_UART2] = {
                "uart2", CGU_CLK_GATE,
-               .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+               .parents = { X1000_CLK_EXCLK },
                .gate = { CGU_REG_CLKGR, 16 },
        },
 
        [X1000_CLK_TCU] = {
                "tcu", CGU_CLK_GATE,
-               .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+               .parents = { X1000_CLK_EXCLK },
                .gate = { CGU_REG_CLKGR, 18 },
        },
 
        [X1000_CLK_SSI] = {
                "ssi", CGU_CLK_GATE,
-               .parents = { X1000_CLK_SSIMUX, -1, -1, -1 },
+               .parents = { X1000_CLK_SSIMUX },
                .gate = { CGU_REG_CLKGR, 19 },
        },
 
        [X1000_CLK_OST] = {
                "ost", CGU_CLK_GATE,
-               .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+               .parents = { X1000_CLK_EXCLK },
                .gate = { CGU_REG_CLKGR, 20 },
        },
 
        [X1000_CLK_PDMA] = {
                "pdma", CGU_CLK_GATE,
-               .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+               .parents = { X1000_CLK_EXCLK },
                .gate = { CGU_REG_CLKGR, 21 },
        },
 };