drm/xe/mocs: Drop HAS_RENDER_L3CC flag
authorMatt Roper <matthew.d.roper@intel.com>
Thu, 23 Feb 2023 18:57:40 +0000 (10:57 -0800)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Tue, 19 Dec 2023 23:29:43 +0000 (18:29 -0500)
The HAS_RENDER_L3CC is set unconditionally so there's no need to keep it
as a dedicated flag.  For error checking purposes, we can just make sure
the 'table' field is initialized properly.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drivers/gpu/drm/xe/xe_mocs.c

index ef237853fdab39450db8364e5a04c8bbd609dbea..e09c6242aafc00005bcf6dc6e930fdb8f7f3ca1f 100644 (file)
@@ -25,7 +25,6 @@ static inline void mocs_dbg(const struct drm_device *dev,
 
 enum {
        HAS_GLOBAL_MOCS = BIT(0),
-       HAS_RENDER_L3CC = BIT(1),
 };
 
 struct xe_mocs_entry {
@@ -440,10 +439,11 @@ static unsigned int get_mocs_settings(struct xe_device *xe,
         */
        XE_WARN_ON(info->unused_entries_index == 0);
 
-       if (XE_WARN_ON(info->size > info->n_entries))
+       if (XE_WARN_ON(info->size > info->n_entries)) {
+               info->table = NULL;
                return 0;
+       }
 
-       flags = HAS_RENDER_L3CC;
        if (!IS_DGFX(xe))
                flags |= HAS_GLOBAL_MOCS;
 
@@ -538,6 +538,6 @@ void xe_mocs_init(struct xe_gt *gt)
         * sure the LNCFCMOCSx registers are programmed for the subsequent
         * memory transactions including guc transactions
         */
-       if (flags & HAS_RENDER_L3CC)
+       if (table.table)
                init_l3cc_table(gt, &table);
 }