drm/sun4i: Add buffer stride and offset configuration for tiling mode

This introduces stride and offset configuration for the VPU tiling mode.
Stride is calculated differently than it is for linear formats and an
offset is calculated, for which new register definitions are introduced.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190118145133.21281-14-paul.kocialkowski@bootlin.com

diff --git a/drivers/gpu/drm/sun4i/sun4i_frontend.c b/drivers/gpu/drm/sun4i/sun4i_frontend.c
index e950370792cefcbf1c3afd5207b44fa7830cce3f..6ede40aab515237d7179e5b363353bec7955cec6 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun4i_frontend.c
+++ b/drivers/gpu/drm/sun4i/sun4i_frontend.c
@@ -126,21 +126,64 @@ void sun4i_frontend_update_buffer(struct sun4i_frontend *frontend,
 {
        struct drm_plane_state *state = plane->state;
        struct drm_framebuffer *fb = state->fb;
+       unsigned int strides[3] = {};
+
        dma_addr_t paddr;
        bool swap;
 
+       if (fb->modifier == DRM_FORMAT_MOD_ALLWINNER_TILED) {
+               unsigned int width = state->src_w >> 16;
+               unsigned int offset;
+
+               strides[0] = SUN4I_FRONTEND_LINESTRD_TILED(fb->pitches[0]);
+
+               /*
+                * The X1 offset is the offset to the bottom-right point in the
+                * end tile, which is the final pixel (at offset width - 1)
+                * within the end tile (with a 32-byte mask).
+                */
+               offset = (width - 1) & (32 - 1);
+
+               regmap_write(frontend->regs, SUN4I_FRONTEND_TB_OFF0_REG,
+                            SUN4I_FRONTEND_TB_OFF_X1(offset));
+
+               if (fb->format->num_planes > 1) {
+                       strides[1] =
+                               SUN4I_FRONTEND_LINESTRD_TILED(fb->pitches[1]);
+
+                       regmap_write(frontend->regs, SUN4I_FRONTEND_TB_OFF1_REG,
+                                    SUN4I_FRONTEND_TB_OFF_X1(offset));
+               }
+
+               if (fb->format->num_planes > 2) {
+                       strides[2] =
+                               SUN4I_FRONTEND_LINESTRD_TILED(fb->pitches[2]);
+
+                       regmap_write(frontend->regs, SUN4I_FRONTEND_TB_OFF2_REG,
+                                    SUN4I_FRONTEND_TB_OFF_X1(offset));
+               }
+       } else {
+               strides[0] = fb->pitches[0];
+
+               if (fb->format->num_planes > 1)
+                       strides[1] = fb->pitches[1];
+
+               if (fb->format->num_planes > 2)
+                       strides[2] = fb->pitches[2];
+       }
+
        /* Set the line width */
        DRM_DEBUG_DRIVER("Frontend stride: %d bytes\n", fb->pitches[0]);
        regmap_write(frontend->regs, SUN4I_FRONTEND_LINESTRD0_REG,
-                    fb->pitches[0]);
+                    strides[0]);
 
        if (fb->format->num_planes > 1)
                regmap_write(frontend->regs, SUN4I_FRONTEND_LINESTRD1_REG,
-                            fb->pitches[1]);
+                            strides[1]);
 
        if (fb->format->num_planes > 2)
                regmap_write(frontend->regs, SUN4I_FRONTEND_LINESTRD2_REG,
-                            fb->pitches[2]);
+                            strides[2]);
 
        /* Some planar formats require chroma channel swapping by hand. */
        swap = sun4i_frontend_format_chroma_requires_swap(fb->format->format);

diff --git a/drivers/gpu/drm/sun4i/sun4i_frontend.h b/drivers/gpu/drm/sun4i/sun4i_frontend.h
index 6c4d7797bb8a91a6fbbd1353e318157e8cdfc14e..235109199b9dd74d7a3f301cb755250f4d039892 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun4i_frontend.h
+++ b/drivers/gpu/drm/sun4i/sun4i_frontend.h
@@ -25,10 +25,29 @@
 #define SUN4I_FRONTEND_BUF_ADDR1_REG           0x024
 #define SUN4I_FRONTEND_BUF_ADDR2_REG           0x028
 
+#define SUN4I_FRONTEND_TB_OFF0_REG             0x030
+#define SUN4I_FRONTEND_TB_OFF1_REG             0x034
+#define SUN4I_FRONTEND_TB_OFF2_REG             0x038
+#define SUN4I_FRONTEND_TB_OFF_X1(x1)                   ((x1) << 16)
+#define SUN4I_FRONTEND_TB_OFF_Y0(y0)                   ((y0) << 8)
+#define SUN4I_FRONTEND_TB_OFF_X0(x0)                   (x0)
+
 #define SUN4I_FRONTEND_LINESTRD0_REG           0x040
 #define SUN4I_FRONTEND_LINESTRD1_REG           0x044
 #define SUN4I_FRONTEND_LINESTRD2_REG           0x048
 
+/*
+ * In tiled mode, the stride is defined as the distance between the start of the
+ * end line of the current tile and the start of the first line in the next
+ * vertical tile.
+ *
+ * Tiles are represented in row-major order, thus the end line of current tile
+ * starts at: 31 * 32 (31 lines of 32 cols), the next vertical tile starts at:
+ * 32-bit-aligned-width * 32 and the distance is:
+ * 32 * (32-bit-aligned-width - 31).
+ */
+#define SUN4I_FRONTEND_LINESTRD_TILED(stride)          (((stride) - 31) * 32)
+
 #define SUN4I_FRONTEND_INPUT_FMT_REG           0x04c
 #define SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_PLANAR       (0 << 8)
 #define SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_PACKED       (1 << 8)