PCI: Add defines for normal and subtractive PCI bridges

Add these PCI class codes to pci_ids.h:

  PCI_CLASS_BRIDGE_PCI_NORMAL
  PCI_CLASS_BRIDGE_PCI_SUBTRACTIVE

Use these defines in all kernel code for describing PCI class codes for
normal and subtractive PCI bridges.

[bhelgaas: similar change in pci-mvebu.c]
Link: https://lore.kernel.org/r/20220214114109.26809-1-pali@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 9ceb5e72889f77c0530be47d38aacd9ad0533731..d3f397dcab6e60d302dfffec7fc200af199ac5f5 100644 (file)
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -1380,8 +1380,6 @@
 
 #define PCIE_IDVAL3_REG                        0x43c
 #define IDVAL3_CLASS_CODE_MASK         0xffffff
-#define IDVAL3_SUBCLASS_SHIFT          8
-#define IDVAL3_CLASS_SHIFT             16
 
 #define PCIE_DLSTATUS_REG              0x1048
 #define DLSTATUS_PHYLINKUP             (1 << 13)

diff --git a/arch/mips/pci/fixup-sb1250.c b/arch/mips/pci/fixup-sb1250.c
index 40efc990cdceb8f1cd448b13ae5ae1d9ba347ed7..3f914c33b7de36b1bb993e54f2db6f638736fc14 100644 (file)
--- a/arch/mips/pci/fixup-sb1250.c
+++ b/arch/mips/pci/fixup-sb1250.c
@@ -75,7 +75,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_PCI,
  */
 static void quirk_sb1250_ht(struct pci_dev *dev)
 {
-       dev->class = PCI_CLASS_BRIDGE_PCI << 8;
+       dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_HT,
                        quirk_sb1250_ht);

diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
index 5548365605c02faa5d82d2b506aedd72b08ff24b..ac83243772d268397da2307801bfdac9cbb4c92c 100644 (file)
--- a/arch/mips/pci/pci-bcm63xx.c
+++ b/arch/mips/pci/pci-bcm63xx.c
@@ -186,7 +186,7 @@ static int __init bcm63xx_register_pcie(void)
        /* setup class code as bridge */
        val = bcm_pcie_readl(PCIE_IDVAL3_REG);
        val &= ~IDVAL3_CLASS_CODE_MASK;
-       val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT);
+       val |= PCI_CLASS_BRIDGE_PCI_NORMAL;
        bcm_pcie_writel(val, PCIE_IDVAL3_REG);
 
        /* disable bar1 size */

diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c
index 9a8391b983d17280b1ee8faa8c9a587c9b4fbcd7..f7054879ecd4bee02676766e1a7033beb57adaa4 100644 (file)
--- a/arch/powerpc/platforms/powernv/pci.c
+++ b/arch/powerpc/platforms/powernv/pci.c
@@ -815,7 +815,7 @@ void pnv_pci_shutdown(void)
 /* Fixup wrong class code in p7ioc and p8 root complex */
 static void pnv_p7ioc_rc_quirk(struct pci_dev *dev)
 {
-       dev->class = PCI_CLASS_BRIDGE_PCI << 8;
+       dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk);
 

diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 674f047b7820af42a05acbb6db87184e480a911b..a97ce602394e580836bf1db2b0831f8c84b6bd77 100644 (file)
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -55,7 +55,7 @@ static void quirk_fsl_pcie_early(struct pci_dev *dev)
        if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
                return;
 
-       dev->class = PCI_CLASS_BRIDGE_PCI << 8;
+       dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
        fsl_pcie_bus_fixup = 1;
        return;
 }

diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c
index 4d499476c33ad6fb18cab4654f3505f6106b288f..b0c2a5238d04974c206cd2eef0642a412c73804c 100644 (file)
--- a/arch/sh/drivers/pci/pcie-sh7786.c
+++ b/arch/sh/drivers/pci/pcie-sh7786.c
@@ -314,7 +314,7 @@ static int __init pcie_init(struct sh7786_pcie_port *port)
         * class to match. Hardware takes care of propagating the IDSETR
         * settings, so there is no need to bother with a quirk.
         */
-       pci_write_reg(chan, PCI_CLASS_BRIDGE_PCI << 16, SH4A_PCIEIDSETR1);
+       pci_write_reg(chan, PCI_CLASS_BRIDGE_PCI_NORMAL << 8, SH4A_PCIEIDSETR1);
 
        /* Initialize default capabilities. */
        data = pci_read_reg(chan, SH4A_PCIEEXPCAP0);

diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
index 1c2ee4e13f1c98937ba08d7ab88ad84b3d3d5107..d10e5fd0f83c8e683e6c5cdc0cf7ff6cac81211f 100644 (file)
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -531,13 +531,13 @@ static void ks_pcie_quirk(struct pci_dev *dev)
        struct pci_dev *bridge;
        static const struct pci_device_id rc_pci_devids[] = {
                { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK),
-                .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
+                .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, },
                { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2E),
-                .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
+                .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, },
                { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L),
-                .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
+                .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, },
                { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2G),
-                .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
+                .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, },
                { 0, },
        };
 

diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c
index 686ded034f224562fd3570d01a2023226515b9c2..f44bf347904adc02e8c181e5433dddf259a2b510 100644 (file)
--- a/drivers/pci/controller/dwc/pci-meson.c
+++ b/drivers/pci/controller/dwc/pci-meson.c
@@ -313,14 +313,14 @@ static int meson_pcie_rd_own_conf(struct pci_bus *bus, u32 devfn,
         * cannot program the PCI_CLASS_DEVICE register, so we must fabricate
         * the return value in the config accessors.
         */
-       if (where == PCI_CLASS_REVISION && size == 4)
-               *val = (PCI_CLASS_BRIDGE_PCI << 16) | (*val & 0xffff);
-       else if (where == PCI_CLASS_DEVICE && size == 2)
-               *val = PCI_CLASS_BRIDGE_PCI;
-       else if (where == PCI_CLASS_DEVICE && size == 1)
-               *val = PCI_CLASS_BRIDGE_PCI & 0xff;
-       else if (where == PCI_CLASS_DEVICE + 1 && size == 1)
-               *val = (PCI_CLASS_BRIDGE_PCI >> 8) & 0xff;
+       if ((where & ~3) == PCI_CLASS_REVISION) {
+               if (size <= 2)
+                       *val = (*val & ((1 << (size * 8)) - 1)) << (8 * (where & 3));
+               *val &= ~0xffffff00;
+               *val |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
+               if (size <= 2)
+                       *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
+       }
 
        return PCIBIOS_SUCCESSFUL;
 }

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index c19cd506ed3f2315312431ca5b9dcf015a4be5f0..a47f1c0434c286124f2a28999f1a3b01569cbfab 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1634,7 +1634,7 @@ static const struct of_device_id qcom_pcie_match[] = {
 
 static void qcom_fixup_class(struct pci_dev *dev)
 {
-       dev->class = PCI_CLASS_BRIDGE_PCI << 8;
+       dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0101, qcom_fixup_class);
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0104, qcom_fixup_class);

diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
index f3547aa60140c4fa61237858490852cf0b1167af..31a7bdebe5403f63f12cf10b329282c6fd35144c 100644 (file)
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
@@ -295,7 +295,7 @@ int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit)
        /* fixup for PCIe class register */
        value = mobiveil_csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);
        value &= 0xff;
-       value |= (PCI_CLASS_BRIDGE_PCI << 16);
+       value |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
        mobiveil_csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
 
        return 0;

diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 4f5b44827d21329d94ffe63a7efd3dc3e08f8283..2561326e9181b5977f768d2c5bef15790d1621e9 100644 (file)
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -529,7 +529,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
         */
        reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG);
        reg &= ~0xffffff00;
-       reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8;
+       reg |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
        advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG);
 
        /* Disable Root Bridge I/O space, memory space and bus mastering */

diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c
index 48169b1e38171d307897db0d355a097c9a0980a2..50a8e1d6f70a188a24aada2050892f4f2f03e4c1 100644 (file)
--- a/drivers/pci/controller/pci-loongson.c
+++ b/drivers/pci/controller/pci-loongson.c
@@ -35,7 +35,7 @@ struct loongson_pci {
 /* Fixup wrong class code in PCIe bridges */
 static void bridge_class_quirk(struct pci_dev *dev)
 {
-       dev->class = PCI_CLASS_BRIDGE_PCI << 8;
+       dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
                        DEV_PCIE_PORT_0, bridge_class_quirk);

diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
index 71258ea3d35f36f618c1f726654833303baa2929..b0ec1c640df77a907f0f67ed244ce96ceda6394d 100644 (file)
--- a/drivers/pci/controller/pci-mvebu.c
+++ b/drivers/pci/controller/pci-mvebu.c
@@ -268,7 +268,7 @@ static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
         */
        dev_rev = mvebu_readl(port, PCIE_DEV_REV_OFF);
        dev_rev &= ~0xffffff00;
-       dev_rev |= (PCI_CLASS_BRIDGE_PCI << 8) << 8;
+       dev_rev |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
        mvebu_writel(port, dev_rev, PCIE_DEV_REV_OFF);
 
        /* Point PCIe unit MBUS decode windows to DRAM space. */

diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
index cb0aa65d6934ae15cdd2fe951be8eb5aef0d6c66..0457ec02ab70607ee9e444f7b4d408d685274e57 100644 (file)
--- a/drivers/pci/controller/pci-tegra.c
+++ b/drivers/pci/controller/pci-tegra.c
@@ -726,7 +726,7 @@ static void tegra_pcie_port_free(struct tegra_pcie_port *port)
 /* Tegra PCIE root complex wrongly reports device class */
 static void tegra_pcie_fixup_class(struct pci_dev *dev)
 {
-       dev->class = PCI_CLASS_BRIDGE_PCI << 8;
+       dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class);
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);

diff --git a/drivers/pci/controller/pcie-iproc-bcma.c b/drivers/pci/controller/pcie-iproc-bcma.c
index 54b6e6d5bc64ca54210c30286e469ec5951db287..99a99900444de1f68503384558e677cac20ae784 100644 (file)
--- a/drivers/pci/controller/pcie-iproc-bcma.c
+++ b/drivers/pci/controller/pcie-iproc-bcma.c
@@ -18,7 +18,7 @@
 /* NS: CLASS field is R/O, and set to wrong 0x200 value */
 static void bcma_pcie2_fixup_class(struct pci_dev *dev)
 {
-       dev->class = PCI_CLASS_BRIDGE_PCI << 8;
+       dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x8011, bcma_pcie2_fixup_class);
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x8012, bcma_pcie2_fixup_class);

diff --git a/drivers/pci/controller/pcie-iproc.c b/drivers/pci/controller/pcie-iproc.c
index b3e75bc61ff177569e411fb3f118828ed59c56db..3df4ab2092539652357969ec596d09baa74b1e0f 100644 (file)
--- a/drivers/pci/controller/pcie-iproc.c
+++ b/drivers/pci/controller/pcie-iproc.c
@@ -1581,7 +1581,7 @@ static void quirk_paxc_bridge(struct pci_dev *pdev)
         * code that the bridge is not an Ethernet device.
         */
        if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
-               pdev->class = PCI_CLASS_BRIDGE_PCI << 8;
+               pdev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
 
        /*
         * MPSS is not being set properly (as it is currently 0).  This is

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
index 7705d61fba4c7a783f4fba15ab9b42b93129bc15..3e8d70bfabc6a913cdd48bcb94a435646b344c30 100644 (file)
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -292,7 +292,7 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
        /* Set class code */
        val = readl_relaxed(pcie->base + PCIE_PCI_IDS_1);
        val &= ~GENMASK(31, 8);
-       val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8);
+       val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI_NORMAL);
        writel_relaxed(val, pcie->base + PCIE_PCI_IDS_1);
 
        /* Mask all INTx interrupts */

diff --git a/drivers/pci/controller/pcie-rcar-host.c b/drivers/pci/controller/pcie-rcar-host.c
index 38b6e02edfa9abcc8a5a9df7cf60ea02334e9dfa..dfca59c4ae34b0ee3bd47b07e5154e15437ad0a8 100644 (file)
--- a/drivers/pci/controller/pcie-rcar-host.c
+++ b/drivers/pci/controller/pcie-rcar-host.c
@@ -370,7 +370,7 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
         * class to match. Hardware takes care of propagating the IDSETR
         * settings, so there is no need to bother with a quirk.
         */
-       rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
+       rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI_NORMAL << 8, IDSETR1);
 
        /*
         * Setup Secondary Bus Number & Subordinate Bus Number, even though

diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c
index 45a28880f32254a7ae269a20293f8b9709e5a75b..7f56f99b4116c882a04e726463a8c7010bb487f0 100644 (file)
--- a/drivers/pci/controller/pcie-rockchip-host.c
+++ b/drivers/pci/controller/pcie-rockchip-host.c
@@ -370,7 +370,7 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip)
        rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,
                            PCIE_CORE_CONFIG_VENDOR);
        rockchip_pcie_write(rockchip,
-                           PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
+                           PCI_CLASS_BRIDGE_PCI_NORMAL << 8,
                            PCIE_RC_CONFIG_RID_CCR);
 
        /* Clear THP cap's next cap pointer to remove L1 substate cap */

diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h
index 1650a5087450b9575f42b1adf93e76264cc9c6ce..32c3a859c26b2113911442bd7f4f57da7952cf0b 100644 (file)
--- a/drivers/pci/controller/pcie-rockchip.h
+++ b/drivers/pci/controller/pcie-rockchip.h
@@ -134,7 +134,6 @@
 #define PCIE_RC_CONFIG_NORMAL_BASE     0x800000
 #define PCIE_RC_CONFIG_BASE            0xa00000
 #define PCIE_RC_CONFIG_RID_CCR         (PCIE_RC_CONFIG_BASE + 0x08)
-#define   PCIE_RC_CONFIG_SCC_SHIFT             16
 #define PCIE_RC_CONFIG_DCR             (PCIE_RC_CONFIG_BASE + 0xc4)
 #define   PCIE_RC_CONFIG_DCR_CSPL_SHIFT                18
 #define   PCIE_RC_CONFIG_DCR_CSPL_LIMIT                0xff

diff --git a/drivers/pci/hotplug/shpchp_core.c b/drivers/pci/hotplug/shpchp_core.c
index 81a918d47895df954d05724262965751ef9baaa7..53692b0483010a623ade83449d2d05abd4fe8bd5 100644 (file)
--- a/drivers/pci/hotplug/shpchp_core.c
+++ b/drivers/pci/hotplug/shpchp_core.c
@@ -312,7 +312,7 @@ static void shpc_remove(struct pci_dev *dev)
 }
 
 static const struct pci_device_id shpcd_pci_tbl[] = {
-       {PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x00), ~0)},
+       {PCI_DEVICE_CLASS(PCI_CLASS_BRIDGE_PCI_NORMAL, ~0)},
        { /* end: all zeroes */ }
 };
 MODULE_DEVICE_TABLE(pci, shpcd_pci_tbl);

diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
index c994ebec2360387755bde3ba5456c6a948a2d587..ec6ab03ae476dee52b403328f41fc40541e0ce1d 100644 (file)
--- a/drivers/pci/pci-bridge-emul.c
+++ b/drivers/pci/pci-bridge-emul.c
@@ -328,10 +328,12 @@ int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
        BUILD_BUG_ON(sizeof(bridge->conf) != PCI_BRIDGE_CONF_END);
 
        /*
-        * class_revision: Class is high 24 bits and revision is low 8 bit of this member,
-        * while class for PCI Bridge Normal Decode has the 24-bit value: PCI_CLASS_BRIDGE_PCI << 8
+        * class_revision: Class is high 24 bits and revision is low 8 bit
+        * of this member, while class for PCI Bridge Normal Decode has the
+        * 24-bit value: PCI_CLASS_BRIDGE_PCI_NORMAL
         */
-       bridge->conf.class_revision |= cpu_to_le32((PCI_CLASS_BRIDGE_PCI << 8) << 8);
+       bridge->conf.class_revision |=
+               cpu_to_le32(PCI_CLASS_BRIDGE_PCI_NORMAL << 8);
        bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;
        bridge->conf.cache_line_size = 0x10;
        bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST);

diff --git a/drivers/pci/pcie/portdrv_pci.c b/drivers/pci/pcie/portdrv_pci.c
index 35eca6277a96ebf63f639a2427b0fa0f25c139be..4b8801656ffbb8fdd3ac43d6b603e42b1a284976 100644 (file)
--- a/drivers/pci/pcie/portdrv_pci.c
+++ b/drivers/pci/pcie/portdrv_pci.c
@@ -178,9 +178,9 @@ static pci_ers_result_t pcie_portdrv_mmio_enabled(struct pci_dev *dev)
  */
 static const struct pci_device_id port_pci_ids[] = {
        /* handle any PCI-Express port */
-       { PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x00), ~0) },
+       { PCI_DEVICE_CLASS(PCI_CLASS_BRIDGE_PCI_NORMAL, ~0) },
        /* subtractive decode PCI-to-PCI bridge, class type is 060401h */
-       { PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x01), ~0) },
+       { PCI_DEVICE_CLASS(PCI_CLASS_BRIDGE_PCI_SUBTRACTIVE, ~0) },
        /* handle any Root Complex Event Collector */
        { PCI_DEVICE_CLASS(((PCI_CLASS_SYSTEM_RCEC << 8) | 0x00), ~0) },
        { },

diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index aad54c66640774643e68910ed23f882a55655592..130949c3b4868ed6647fdc103a241c767e82aa95 100644 (file)
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -60,6 +60,8 @@
 #define PCI_CLASS_BRIDGE_EISA          0x0602
 #define PCI_CLASS_BRIDGE_MC            0x0603
 #define PCI_CLASS_BRIDGE_PCI           0x0604
+#define PCI_CLASS_BRIDGE_PCI_NORMAL            0x060400
+#define PCI_CLASS_BRIDGE_PCI_SUBTRACTIVE       0x060401
 #define PCI_CLASS_BRIDGE_PCMCIA                0x0605
 #define PCI_CLASS_BRIDGE_NUBUS         0x0606
 #define PCI_CLASS_BRIDGE_CARDBUS       0x0607