iio: adc: ad7923: Fix alignment for DMA safety

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Update the comment to include 'may'.

Note that some other fixes have applied to this line of code
that may complicate automated backporting.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Fixes: 0eac259db28f ("IIO ADC support for AD7923")
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-19-jic23@kernel.org

diff --git a/drivers/iio/adc/ad7923.c b/drivers/iio/adc/ad7923.c
index 069b561ee76896fb3a4b24fb63c6c70f88f7c9ed..edad1f30121dd9c8206b8e6b72e09cb7babfe64a 100644 (file)
--- a/drivers/iio/adc/ad7923.c
+++ b/drivers/iio/adc/ad7923.c
@@ -57,12 +57,12 @@ struct ad7923_state {
        unsigned int                    settings;
 
        /*
-        * DMA (thus cache coherency maintenance) requires the
+        * DMA (thus cache coherency maintenance) may require the
         * transfer buffers to live in their own cache lines.
         * Ensure rx_buf can be directly used in iio_push_to_buffers_with_timetamp
         * Length = 8 channels + 4 extra for 8 byte timestamp
         */
-       __be16                          rx_buf[12] ____cacheline_aligned;
+       __be16                          rx_buf[12] __aligned(IIO_DMA_MINALIGN);
        __be16                          tx_buf[4];
 };