arm64/sysreg: Rename TRBBASER_EL1 fields per auto-gen tools format

This renames TRBBASER_EL1 register fields per auto-gen tools format without
causing any functional change in the TRBE driver.

Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: kvmarm@lists.linux.dev
Cc: coresight@lists.linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20230614065949.146187-4-anshuman.khandual@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 31005f72353e24b0f33f71af918f903210bfa4b6..80780dec31d08aafdf37d6b7c1431ee3b777fd42 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -248,8 +248,8 @@
 #define TRBLIMITR_EL1_E                        BIT(0)
 #define TRBPTR_EL1_PTR_MASK            GENMASK_ULL(63, 0)
 #define TRBPTR_EL1_PTR_SHIFT           0
-#define TRBBASER_BASE_MASK             GENMASK_ULL(51, 0)
-#define TRBBASER_BASE_SHIFT            12
+#define TRBBASER_EL1_BASE_MASK         GENMASK_ULL(63, 12)
+#define TRBBASER_EL1_BASE_SHIFT                12
 #define TRBSR_EC_MASK                  GENMASK(5, 0)
 #define TRBSR_EC_SHIFT                 26
 #define TRBSR_IRQ                      BIT(22)

diff --git a/drivers/hwtracing/coresight/coresight-trbe.h b/drivers/hwtracing/coresight/coresight-trbe.h
index 8ea7079d60bb2e928933cbddd55f83a74fa73620..0b73d9d10aa87baf120cc53b81186c36e765d237 100644 (file)
--- a/drivers/hwtracing/coresight/coresight-trbe.h
+++ b/drivers/hwtracing/coresight/coresight-trbe.h
@@ -131,7 +131,7 @@ static inline unsigned long get_trbe_limit_pointer(void)
 static inline unsigned long get_trbe_base_pointer(void)
 {
        u64 trbbaser = read_sysreg_s(SYS_TRBBASER_EL1);
-       unsigned long addr = trbbaser & (TRBBASER_BASE_MASK << TRBBASER_BASE_SHIFT);
+       unsigned long addr = trbbaser & TRBBASER_EL1_BASE_MASK;
 
        WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
        return addr;
@@ -140,7 +140,7 @@ static inline unsigned long get_trbe_base_pointer(void)
 static inline void set_trbe_base_pointer(unsigned long addr)
 {
        WARN_ON(is_trbe_enabled());
-       WARN_ON(!IS_ALIGNED(addr, (1UL << TRBBASER_BASE_SHIFT)));
+       WARN_ON(!IS_ALIGNED(addr, (1UL << TRBBASER_EL1_BASE_SHIFT)));
        WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
        write_sysreg_s(addr, SYS_TRBBASER_EL1);
 }