RISC-V: KVM: Allow Zbb extension for Guest/VM
authorAnup Patel <apatel@ventanamicro.com>
Sat, 1 Apr 2023 09:51:34 +0000 (15:21 +0530)
committerAnup Patel <anup@brainfault.org>
Fri, 21 Apr 2023 12:08:46 +0000 (17:38 +0530)
We extend the KVM ISA extension ONE_REG interface to allow KVM
user space to detect and enable Zbb extension for Guest/VM.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
arch/riscv/include/uapi/asm/kvm.h
arch/riscv/kvm/vcpu.c

index d8ead5952ed9caaefa59f0ba1d09518b7c1f52c5..47a7c3958229eff0955637377b72bdf74414eef4 100644 (file)
@@ -106,6 +106,7 @@ enum KVM_RISCV_ISA_EXT_ID {
        KVM_RISCV_ISA_EXT_SVINVAL,
        KVM_RISCV_ISA_EXT_ZIHINTPAUSE,
        KVM_RISCV_ISA_EXT_ZICBOM,
+       KVM_RISCV_ISA_EXT_ZBB,
        KVM_RISCV_ISA_EXT_MAX,
 };
 
index 3112697cb12d97d4da9a85d2c646ab61af414cd0..02b49cb9456198d351ed2b15a0f24c418b689ece 100644 (file)
@@ -61,6 +61,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
        KVM_ISA_EXT_ARR(SSTC),
        KVM_ISA_EXT_ARR(SVINVAL),
        KVM_ISA_EXT_ARR(SVPBMT),
+       KVM_ISA_EXT_ARR(ZBB),
        KVM_ISA_EXT_ARR(ZIHINTPAUSE),
        KVM_ISA_EXT_ARR(ZICBOM),
 };
@@ -99,6 +100,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
        case KVM_RISCV_ISA_EXT_SSTC:
        case KVM_RISCV_ISA_EXT_SVINVAL:
        case KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
+       case KVM_RISCV_ISA_EXT_ZBB:
                return false;
        default:
                break;