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ARM: dts: sun8i: V3/V3s/S3/S3L: add CSI1 device node
author
Icenowy Zheng
<icenowy@aosc.io>
Wed, 23 Sep 2020 00:58:54 +0000
(08:58 +0800)
committer
Maxime Ripard
<maxime@cerno.tech>
Mon, 28 Sep 2020 10:09:22 +0000
(12:09 +0200)
The CSI1 controller of V3/V3s/S3/S3L chips is used for parallel CSI.
Add the device tree node of it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link:
https://lore.kernel.org/r/20200923005858.148261-2-icenowy@aosc.io
arch/arm/boot/dts/sun8i-v3s.dtsi
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diff --git
a/arch/arm/boot/dts/sun8i-v3s.dtsi
b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 4cfdf193cf88ec15d3fb02f9f221b8b19a794bf0..3e079973672df3b08fea7f60f4c61919f0ba7691 100644
(file)
--- a/
arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/
arch/arm/boot/dts/sun8i-v3s.dtsi
@@
-488,6
+488,18
@@
#size-cells = <0>;
};
+ csi1: camera@1cb4000 {
+ compatible = "allwinner,sun8i-v3s-csi";
+ reg = <0x01cb4000 0x3000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CSI>,
+ <&ccu CLK_CSI1_SCLK>,
+ <&ccu CLK_DRAM_CSI>;
+ clock-names = "bus", "mod", "ram";
+ resets = <&ccu RST_BUS_CSI>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@1c81000 {
compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,