arm64: dts: amazon: alpine-v2: move non-MMIO node out of soc

Non-MMIO devices should not be within simple-bus, as reported by dtc W=1
warning:

  alpine-v2.dtsi:100.9-106.5: Warning (simple_bus_reg): /soc/timer: missing or empty reg/ranges property
  alpine-v2.dtsi:108.7-114.5: Warning (simple_bus_reg): /soc/pmu: missing or empty reg/ranges property

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20240402200744.79349-2-krzk@kernel.org

diff --git a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi
index 32b6ac8a5352973457a48b57c0f8f7678525becf..5b6b58dd44cb9e092756b2ecae49b647fed9d73d 100644 (file)
--- a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi
+++ b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi
@@ -39,6 +39,7 @@
 / {
        model = "Annapurna Labs Alpine v2";
        compatible = "al,alpine-v2";
+       interrupt-parent = <&gic>;
        #address-cells = <2>;
        #size-cells = <2>;
 
@@ -89,6 +90,22 @@
                clock-frequency = <1000000>;
        };
 
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+       };
+
+       pmu {
+               compatible = "arm,armv8-pmuv3";
+               interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+       };
+
        soc {
                compatible = "simple-bus";
                #address-cells = <2>;
@@ -97,22 +114,6 @@
                interrupt-parent = <&gic>;
                ranges;
 
-               timer {
-                       compatible = "arm,armv8-timer";
-                       interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-                                    <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
-                                    <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
-                                    <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
-               };
-
-               pmu {
-                       compatible = "arm,armv8-pmuv3";
-                       interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-               };
-
                gic: interrupt-controller@f0200000 {
                        compatible = "arm,gic-v3";
                        reg = <0x0 0xf0200000 0x0 0x10000>,     /* GIC Dist */