arm64: dts: rockchip: Add RK3399-T OPP table
authorJagan Teki <jagan@amarulasolutions.com>
Fri, 2 Sep 2022 06:50:56 +0000 (12:20 +0530)
committerHeiko Stuebner <heiko@sntech.de>
Mon, 5 Sep 2022 10:10:20 +0000 (12:10 +0200)
RK3399-T is down-clocked version of RK3399 SoC operated at 1.5GHz.

Add CPU operating points table for it.

Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Link: https://lore.kernel.org/r/20220902065057.97425-2-jagan@amarulasolutions.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm64/boot/dts/rockchip/rk3399-t-opp.dtsi [new file with mode: 0644]

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-t-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-t-opp.dtsi
new file mode 100644 (file)
index 0000000..1ababad
--- /dev/null
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2022 Radxa Limited
+ */
+
+/ {
+       cluster0_opp: opp-table-0 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp00 {
+                       opp-hz = /bits/ 64 <408000000>;
+                       opp-microvolt = <875000 875000 1250000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp01 {
+                       opp-hz = /bits/ 64 <600000000>;
+                       opp-microvolt = <875000 875000 1250000>;
+               };
+               opp02 {
+                       opp-hz = /bits/ 64 <816000000>;
+                       opp-microvolt = <900000 900000 1250000>;
+               };
+               opp03 {
+                       opp-hz = /bits/ 64 <1008000000>;
+                       opp-microvolt = <975000 975000 1250000>;
+               };
+       };
+
+       cluster1_opp: opp-table-1 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp00 {
+                       opp-hz = /bits/ 64 <408000000>;
+                       opp-microvolt = <875000 875000 1250000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp01 {
+                       opp-hz = /bits/ 64 <600000000>;
+                       opp-microvolt = <875000 875000 1250000>;
+               };
+               opp02 {
+                       opp-hz = /bits/ 64 <816000000>;
+                       opp-microvolt = <875000 875000 1250000>;
+               };
+               opp03 {
+                       opp-hz = /bits/ 64 <1008000000>;
+                       opp-microvolt = <925000 925000 1250000>;
+               };
+               opp04 {
+                       opp-hz = /bits/ 64 <1200000000>;
+                       opp-microvolt = <1000000 1000000 1250000>;
+               };
+               opp05 {
+                       opp-hz = /bits/ 64 <1416000000>;
+                       opp-microvolt = <1075000 1075000 1250000>;
+               };
+               opp06 {
+                       opp-hz = /bits/ 64 <1512000000>;
+                       opp-microvolt = <1150000 1150000 1250000>;
+               };
+       };
+
+       gpu_opp_table: opp-table-2 {
+               compatible = "operating-points-v2";
+
+               opp00 {
+                       opp-hz = /bits/ 64 <200000000>;
+                       opp-microvolt = <875000 875000 1150000>;
+               };
+               opp01 {
+                       opp-hz = /bits/ 64 <300000000>;
+                       opp-microvolt = <875000 875000 1150000>;
+               };
+               opp02 {
+                       opp-hz = /bits/ 64 <400000000>;
+                       opp-microvolt = <875000 875000 1150000>;
+               };
+               opp03 {
+                       opp-hz = /bits/ 64 <600000000>;
+                       opp-microvolt = <975000 975000 1150000>;
+               };
+       };
+};
+
+&cpu_l0 {
+       operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_l1 {
+       operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_l2 {
+       operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_l3 {
+       operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_b0 {
+       operating-points-v2 = <&cluster1_opp>;
+};
+
+&cpu_b1 {
+       operating-points-v2 = <&cluster1_opp>;
+};
+
+&gpu {
+       operating-points-v2 = <&gpu_opp_table>;
+};