#define REVID_SHIFT 16
#define REVID_MASK GENMASK(31, 16)
+#define CAPLIST 0x004
+#define CAPLIST_ID_SHIFT 16
+#define CAPLIST_ID_MASK GENMASK(23, 16)
+#define CAPLIST_ID_GPIO_HW_INFO 1
+#define CAPLIST_ID_PWM 2
+#define CAPLIST_ID_BLINK 3
+#define CAPLIST_ID_EXP 4
+#define CAPLIST_NEXT_SHIFT 0
+#define CAPLIST_NEXT_MASK GENMASK(15, 0)
+
#define PADBAR 0x00c
#define PADOWN_BITS 4
for (i = 0; i < pctrl->ncommunities; i++) {
struct intel_community *community = &pctrl->communities[i];
void __iomem *regs;
- u32 padbar;
+ u32 offset;
u32 value;
*community = pctrl->soc->communities[i];
community->features |= PINCTRL_FEATURE_1K_PD;
}
+ /* Determine community features based on the capabilities */
+ offset = CAPLIST;
+ do {
+ value = readl(regs + offset);
+ switch ((value & CAPLIST_ID_MASK) >> CAPLIST_ID_SHIFT) {
+ case CAPLIST_ID_GPIO_HW_INFO:
+ community->features |= PINCTRL_FEATURE_GPIO_HW_INFO;
+ break;
+ case CAPLIST_ID_PWM:
+ community->features |= PINCTRL_FEATURE_PWM;
+ break;
+ case CAPLIST_ID_BLINK:
+ community->features |= PINCTRL_FEATURE_BLINK;
+ break;
+ case CAPLIST_ID_EXP:
+ community->features |= PINCTRL_FEATURE_EXP;
+ break;
+ default:
+ break;
+ }
+ offset = (value & CAPLIST_NEXT_MASK) >> CAPLIST_NEXT_SHIFT;
+ } while (offset);
+
+ dev_dbg(&pdev->dev, "Community%d features: %#08x\n", i, community->features);
+
/* Read offset of the pad configuration registers */
- padbar = readl(regs + PADBAR);
+ offset = readl(regs + PADBAR);
community->regs = regs;
- community->pad_regs = regs + padbar;
+ community->pad_regs = regs + offset;
if (community->gpps)
ret = intel_pinctrl_add_padgroups_by_gpps(pctrl, community);
/* Additional features supported by the hardware */
#define PINCTRL_FEATURE_DEBOUNCE BIT(0)
#define PINCTRL_FEATURE_1K_PD BIT(1)
+#define PINCTRL_FEATURE_GPIO_HW_INFO BIT(2)
+#define PINCTRL_FEATURE_PWM BIT(3)
+#define PINCTRL_FEATURE_BLINK BIT(4)
+#define PINCTRL_FEATURE_EXP BIT(5)
/**
* PIN_GROUP - Declare a pin group