ARM: mstar: Add interrupt controller to base dtsi

Add the IRQ and FIQ intc instances to the base MStar/SigmaStar v7
dtsi. All of the known SoCs have both and at the same place with
their common IPs using the same interrupt lines.

Link: https://lore.kernel.org/r/20201002133418.2250277-3-daniel@0x0f.com
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi
index 3b7b9b793736d632d71e8365c1d108855827ceb4..aec841b52ca4dfefdb5cf7ce7868a1b6fb5191f4 100644 (file)
--- a/arch/arm/boot/dts/mstar-v7.dtsi
+++ b/arch/arm/boot/dts/mstar-v7.dtsi
@@ -85,6 +85,25 @@
                                mask = <0x79>;
                        };
 
+                       intc_fiq: interrupt-controller@201310 {
+                               compatible = "mstar,mst-intc";
+                               reg = <0x201310 0x40>;
+                               #interrupt-cells = <3>;
+                               interrupt-controller;
+                               interrupt-parent = <&gic>;
+                               mstar,irqs-map-range = <96 127>;
+                       };
+
+                       intc_irq: interrupt-controller@201350 {
+                               compatible = "mstar,mst-intc";
+                               reg = <0x201350 0x40>;
+                               #interrupt-cells = <3>;
+                               interrupt-controller;
+                               interrupt-parent = <&gic>;
+                               mstar,irqs-map-range = <32 95>;
+                               mstar,intc-no-eoi;
+                       };
+
                        l3bridge: l3bridge@204400 {
                                compatible = "mstar,l3bridge";
                                reg = <0x204400 0x200>;