spi: intel: Use correct mask for flash and protected regions

The flash and protected region mask is actually 0x7fff (30:16 and 14:0)
and not 0x3fff so fix this accordingly. While there use GENMASK() instead.

Cc: stable@vger.kernel.org
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20221025062800.22357-1-mika.westerberg@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-intel.c b/drivers/spi/spi-intel.c
index 605acb1bf4b08e83c158c5871a1e3e8d8b7a9193..3ac73691fbb549604e06d4f787c6b8f9b89e352f 100644 (file)
--- a/drivers/spi/spi-intel.c
+++ b/drivers/spi/spi-intel.c
@@ -52,17 +52,17 @@
 #define FRACC                          0x50
 
 #define FREG(n)                                (0x54 + ((n) * 4))
-#define FREG_BASE_MASK                 0x3fff
+#define FREG_BASE_MASK                 GENMASK(14, 0)
 #define FREG_LIMIT_SHIFT               16
-#define FREG_LIMIT_MASK                        (0x03fff << FREG_LIMIT_SHIFT)
+#define FREG_LIMIT_MASK                        GENMASK(30, 16)
 
 /* Offset is from @ispi->pregs */
 #define PR(n)                          ((n) * 4)
 #define PR_WPE                         BIT(31)
 #define PR_LIMIT_SHIFT                 16
-#define PR_LIMIT_MASK                  (0x3fff << PR_LIMIT_SHIFT)
+#define PR_LIMIT_MASK                  GENMASK(30, 16)
 #define PR_RPE                         BIT(15)
-#define PR_BASE_MASK                   0x3fff
+#define PR_BASE_MASK                   GENMASK(14, 0)
 
 /* Offsets are from @ispi->sregs */
 #define SSFSTS_CTL                     0x00