arm64: dts: renesas: rzg3s-smarc-som: Enable the Ethernet interfaces

The RZ/G3S Smarc Module has Ethernet PHYs (KSZ9131) connected to each
Ethernet IP.  For this, add proper DT descriptions to enable Ethernet
communication through these PHYs.

The interface b/w PHYs and MACs is RGMII.  The skew settings were set to
zero as based on phy-mode (rgmii-id) the KSZ9131 driver enables internal
DLL, which adds a 2ns delay b/w clocks (TX/RX) and data signals.

Different pin settings were applied to TXC and TX_CTL compared with the
rest of the RGMII pins to comply with requirements for these pins
imposed by HW manual of RZ/G3S (see chapters "Ether Ch0 Voltage Mode
Control Register (ETH0_POC)", "Ether Ch1 Voltage Mode Control Register
(ETH1_POC)", for power source selection, "Ether MII/RGMII Mode Control
Register (ETH_MODE)" for output-enable and "Input Enable Control
Register (IEN_m)" for input-enable configurations).

Also enable the Ethernet interfaces by selecting SW_CONFIG3 = SW_ON.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231207070700.4156557-12-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
index f59094701a4a4fc20a4610a636e667be3baf0145..f062d4ad78b79d9a2c511b31bd2159e9c89d6e87 100644 (file)
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
@@ -26,7 +26,7 @@
  *     SW_ON  - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC
  */
 #define SW_CONFIG2     SW_ON
-#define SW_CONFIG3     SW_OFF
+#define SW_CONFIG3     SW_ON
 
 / {
        compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045";
@@ -35,6 +35,9 @@
                mmc0 = &sdhi0;
 #if SW_CONFIG3 == SW_OFF
                mmc2 = &sdhi2;
+#else
+               eth0 = &eth0;
+               eth1 = &eth1;
 #endif
        };
 
@@ -89,6 +92,60 @@
        };
 };
 
+#if SW_CONFIG3 == SW_ON
+&eth0 {
+       pinctrl-0 = <&eth0_pins>;
+       pinctrl-names = "default";
+       phy-handle = <&phy0>;
+       phy-mode = "rgmii-id";
+       status = "okay";
+
+       phy0: ethernet-phy@7 {
+               reg = <7>;
+               interrupt-parent = <&pinctrl>;
+               interrupts = <RZG2L_GPIO(12, 0) IRQ_TYPE_EDGE_FALLING>;
+               rxc-skew-psec = <0>;
+               txc-skew-psec = <0>;
+               rxdv-skew-psec = <0>;
+               txen-skew-psec = <0>;
+               rxd0-skew-psec = <0>;
+               rxd1-skew-psec = <0>;
+               rxd2-skew-psec = <0>;
+               rxd3-skew-psec = <0>;
+               txd0-skew-psec = <0>;
+               txd1-skew-psec = <0>;
+               txd2-skew-psec = <0>;
+               txd3-skew-psec = <0>;
+       };
+};
+
+&eth1 {
+       pinctrl-0 = <&eth1_pins>;
+       pinctrl-names = "default";
+       phy-handle = <&phy1>;
+       phy-mode = "rgmii-id";
+       status = "okay";
+
+       phy1: ethernet-phy@7 {
+               reg = <7>;
+               interrupt-parent = <&pinctrl>;
+               interrupts = <RZG2L_GPIO(12, 1) IRQ_TYPE_EDGE_FALLING>;
+               rxc-skew-psec = <0>;
+               txc-skew-psec = <0>;
+               rxdv-skew-psec = <0>;
+               txen-skew-psec = <0>;
+               rxd0-skew-psec = <0>;
+               rxd1-skew-psec = <0>;
+               rxd2-skew-psec = <0>;
+               rxd3-skew-psec = <0>;
+               txd0-skew-psec = <0>;
+               txd1-skew-psec = <0>;
+               txd2-skew-psec = <0>;
+               txd3-skew-psec = <0>;
+       };
+};
+#endif
+
 &extal_clk {
        clock-frequency = <24000000>;
 };
@@ -136,6 +193,88 @@
 #endif
 
 &pinctrl {
+       eth0-phy-irq-hog {
+               gpio-hog;
+               gpios = <RZG2L_GPIO(12, 0) GPIO_ACTIVE_LOW>;
+               input;
+               line-name = "eth0-phy-irq";
+       };
+
+       eth0_pins: eth0 {
+               txc {
+                       pinmux = <RZG2L_PORT_PINMUX(1, 0, 1)>;  /* ET0_TXC */
+                       power-source = <1800>;
+                       output-enable;
+                       input-enable;
+                       drive-strength-microamp = <5200>;
+               };
+
+               tx_ctl {
+                       pinmux = <RZG2L_PORT_PINMUX(1, 1, 1)>;  /* ET0_TX_CTL */
+                       power-source = <1800>;
+                       output-enable;
+                       drive-strength-microamp = <5200>;
+               };
+
+               mux {
+                       pinmux = <RZG2L_PORT_PINMUX(1, 2, 1)>,  /* ET0_TXD0 */
+                                <RZG2L_PORT_PINMUX(1, 3, 1)>,  /* ET0_TXD1 */
+                                <RZG2L_PORT_PINMUX(1, 4, 1)>,  /* ET0_TXD2 */
+                                <RZG2L_PORT_PINMUX(2, 0, 1)>,  /* ET0_TXD3 */
+                                <RZG2L_PORT_PINMUX(3, 0, 1)>,  /* ET0_RXC */
+                                <RZG2L_PORT_PINMUX(3, 1, 1)>,  /* ET0_RX_CTL */
+                                <RZG2L_PORT_PINMUX(3, 2, 1)>,  /* ET0_RXD0 */
+                                <RZG2L_PORT_PINMUX(3, 3, 1)>,  /* ET0_RXD1 */
+                                <RZG2L_PORT_PINMUX(4, 0, 1)>,  /* ET0_RXD2 */
+                                <RZG2L_PORT_PINMUX(4, 1, 1)>,  /* ET0_RXD3 */
+                                <RZG2L_PORT_PINMUX(4, 3, 1)>,  /* ET0_MDC */
+                                <RZG2L_PORT_PINMUX(4, 4, 1)>,  /* ET0_MDIO */
+                                <RZG2L_PORT_PINMUX(4, 5, 1)>;  /* ET0_LINKSTA */
+                       power-source = <1800>;
+               };
+       };
+
+       eth1-phy-irq-hog {
+               gpio-hog;
+               gpios = <RZG2L_GPIO(12, 1) GPIO_ACTIVE_LOW>;
+               input;
+               line-name = "eth1-phy-irq";
+       };
+
+       eth1_pins: eth1 {
+               txc {
+                       pinmux = <RZG2L_PORT_PINMUX(7, 0, 1)>;  /* ET1_TXC */
+                       power-source = <1800>;
+                       output-enable;
+                       input-enable;
+                       drive-strength-microamp = <5200>;
+               };
+
+               tx_ctl {
+                       pinmux = <RZG2L_PORT_PINMUX(7, 1, 1)>;  /* ET1_TX_CTL */
+                       power-source = <1800>;
+                       output-enable;
+                       drive-strength-microamp = <5200>;
+               };
+
+               mux {
+                       pinmux = <RZG2L_PORT_PINMUX(7, 2, 1)>,  /* ET1_TXD0 */
+                                <RZG2L_PORT_PINMUX(7, 3, 1)>,  /* ET1_TXD1 */
+                                <RZG2L_PORT_PINMUX(7, 4, 1)>,  /* ET1_TXD2 */
+                                <RZG2L_PORT_PINMUX(8, 0, 1)>,  /* ET1_TXD3 */
+                                <RZG2L_PORT_PINMUX(8, 4, 1)>,  /* ET1_RXC */
+                                <RZG2L_PORT_PINMUX(9, 0, 1)>,  /* ET1_RX_CTL */
+                                <RZG2L_PORT_PINMUX(9, 1, 1)>,  /* ET1_RXD0 */
+                                <RZG2L_PORT_PINMUX(9, 2, 1)>,  /* ET1_RXD1 */
+                                <RZG2L_PORT_PINMUX(9, 3, 1)>,  /* ET1_RXD2 */
+                                <RZG2L_PORT_PINMUX(10, 0, 1)>, /* ET1_RXD3 */
+                                <RZG2L_PORT_PINMUX(10, 2, 1)>, /* ET1_MDC */
+                                <RZG2L_PORT_PINMUX(10, 3, 1)>, /* ET1_MDIO */
+                                <RZG2L_PORT_PINMUX(10, 4, 1)>; /* ET1_LINKSTA */
+                       power-source = <1800>;
+               };
+       };
+
        sdhi0_pins: sd0 {
                data {
                        pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";