arm64: dts: qcom: sc7280: Fix up GPU SIDs

GPU_SMMU SID 1 is meant for Adreno LPAC (Low Priority Async Compute).
On platforms that support it (in firmware), it is necessary to
describe that link, or Adreno register access will hang the board.

The current settings are functionally identical, *but* due to what is
likely hardcoded security policies, the secure firmware rejects them,
resulting in the board hanging. To avoid that, alter the settings such
that SID 0 and 1 are described separately.

Fixes: 96c471970b7b ("arm64: dts: qcom: sc7280: Add gpu support")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230926-topic-a643-v2-2-06fa3d899c0a@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 8af11b8cbdc09ac8298e475ada5f71f57f28121b..7ee703f9a16ef4593c7c057209604e42ebd9c32a 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2609,7 +2609,8 @@
                                    "cx_mem",
                                    "cx_dbgc";
                        interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
-                       iommus = <&adreno_smmu 0 0x401>;
+                       iommus = <&adreno_smmu 0 0x400>,
+                                <&adreno_smmu 1 0x400>;
                        operating-points-v2 = <&gpu_opp_table>;
                        qcom,gmu = <&gmu>;
                        interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;