tools/power/turbostat: Adjust cstate for has_snb_msrs() models

Enable CC7 and PC2 for has_snb_msrs() models.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Len Brown <len.brown@intel.com>

diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c
index c7345e0c5185efc6215ac05042b6ee1590dd610f..174a8d0750da5743c19daae76ace87f966596eeb 100644 (file)
--- a/tools/power/x86/turbostat/turbostat.c
+++ b/tools/power/x86/turbostat/turbostat.c
@@ -434,7 +434,7 @@ static const struct platform_features snb_features = {
        .has_msr_misc_pwr_mgmt = 1,
        .has_nhm_msrs = 1,
        .bclk_freq = BCLK_100MHZ,
-       .supported_cstates = CC1 | CC3 | CC6,
+       .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2,
        .cst_limit = CST_LIMIT_SNB,
        .trl_msrs = TRL_BASE,
        .rapl_msrs = RAPL_PKG | RAPL_CORE_ALL | RAPL_GFX | RAPL_PKG_POWER_INFO,
@@ -445,7 +445,7 @@ static const struct platform_features snx_features = {
        .has_msr_misc_pwr_mgmt = 1,
        .has_nhm_msrs = 1,
        .bclk_freq = BCLK_100MHZ,
-       .supported_cstates = CC1 | CC3 | CC6,
+       .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2,
        .cst_limit = CST_LIMIT_SNB,
        .trl_msrs = TRL_BASE,
        .rapl_msrs = RAPL_PKG_ALL | RAPL_CORE_ALL | RAPL_DRAM_ALL,
@@ -457,7 +457,7 @@ static const struct platform_features ivb_features = {
        .has_nhm_msrs = 1,
        .has_config_tdp = 1,
        .bclk_freq = BCLK_100MHZ,
-       .supported_cstates = CC1 | CC3 | CC6,
+       .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2,
        .cst_limit = CST_LIMIT_SNB,
        .trl_msrs = TRL_BASE,
        .rapl_msrs = RAPL_PKG | RAPL_CORE_ALL | RAPL_GFX | RAPL_PKG_POWER_INFO,
@@ -468,7 +468,7 @@ static const struct platform_features ivx_features = {
        .has_msr_misc_pwr_mgmt = 1,
        .has_nhm_msrs = 1,
        .bclk_freq = BCLK_100MHZ,
-       .supported_cstates = CC1 | CC3 | CC6,
+       .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2,
        .cst_limit = CST_LIMIT_SNB,
        .trl_msrs = TRL_BASE | TRL_LIMIT1,
        .rapl_msrs = RAPL_PKG_ALL | RAPL_CORE_ALL | RAPL_DRAM_ALL,
@@ -480,7 +480,7 @@ static const struct platform_features hsw_features = {
        .has_nhm_msrs = 1,
        .has_config_tdp = 1,
        .bclk_freq = BCLK_100MHZ,
-       .supported_cstates = CC1 | CC3 | CC6,
+       .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2,
        .cst_limit = CST_LIMIT_HSW,
        .trl_msrs = TRL_BASE,
        .plr_msrs = PLR_CORE | PLR_GFX | PLR_RING,
@@ -493,7 +493,7 @@ static const struct platform_features hsx_features = {
        .has_nhm_msrs = 1,
        .has_config_tdp = 1,
        .bclk_freq = BCLK_100MHZ,
-       .supported_cstates = CC1 | CC3 | CC6,
+       .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2,
        .cst_limit = CST_LIMIT_HSW,
        .trl_msrs = TRL_BASE | TRL_LIMIT1 | TRL_LIMIT2,
        .plr_msrs = PLR_CORE | PLR_RING,
@@ -507,7 +507,7 @@ static const struct platform_features hswl_features = {
        .has_nhm_msrs = 1,
        .has_config_tdp = 1,
        .bclk_freq = BCLK_100MHZ,
-       .supported_cstates = CC1 | CC3 | CC6,
+       .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2,
        .cst_limit = CST_LIMIT_HSW,
        .trl_msrs = TRL_BASE,
        .plr_msrs = PLR_CORE | PLR_GFX | PLR_RING,
@@ -520,7 +520,7 @@ static const struct platform_features hswg_features = {
        .has_nhm_msrs = 1,
        .has_config_tdp = 1,
        .bclk_freq = BCLK_100MHZ,
-       .supported_cstates = CC1 | CC3 | CC6,
+       .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2,
        .cst_limit = CST_LIMIT_HSW,
        .trl_msrs = TRL_BASE,
        .plr_msrs = PLR_CORE | PLR_GFX | PLR_RING,
@@ -533,7 +533,7 @@ static const struct platform_features bdw_features = {
        .has_nhm_msrs = 1,
        .has_config_tdp = 1,
        .bclk_freq = BCLK_100MHZ,
-       .supported_cstates = CC1 | CC3 | CC6,
+       .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2,
        .cst_limit = CST_LIMIT_HSW,
        .trl_msrs = TRL_BASE,
        .rapl_msrs = RAPL_PKG | RAPL_CORE_ALL | RAPL_GFX | RAPL_PKG_POWER_INFO,
@@ -545,7 +545,7 @@ static const struct platform_features bdwg_features = {
        .has_nhm_msrs = 1,
        .has_config_tdp = 1,
        .bclk_freq = BCLK_100MHZ,
-       .supported_cstates = CC1 | CC3 | CC6,
+       .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2,
        .cst_limit = CST_LIMIT_HSW,
        .trl_msrs = TRL_BASE,
        .rapl_msrs = RAPL_PKG | RAPL_CORE_ALL | RAPL_GFX | RAPL_PKG_POWER_INFO,
@@ -557,7 +557,7 @@ static const struct platform_features bdx_features = {
        .has_nhm_msrs = 1,
        .has_config_tdp = 1,
        .bclk_freq = BCLK_100MHZ,
-       .supported_cstates = CC1 | CC3 | CC6,
+       .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2,
        .cst_limit = CST_LIMIT_HSW,
        .has_cst_auto_convension = 1,
        .trl_msrs = TRL_BASE,
@@ -572,7 +572,7 @@ static const struct platform_features skl_features = {
        .has_config_tdp = 1,
        .bclk_freq = BCLK_100MHZ,
        .crystal_freq = 24000000,
-       .supported_cstates = CC1 | CC3 | CC6,
+       .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2,
        .cst_limit = CST_LIMIT_HSW,
        .trl_msrs = TRL_BASE,
        .tcc_offset_bits = 6,
@@ -586,7 +586,7 @@ static const struct platform_features cnl_features = {
        .has_nhm_msrs = 1,
        .has_config_tdp = 1,
        .bclk_freq = BCLK_100MHZ,
-       .supported_cstates = CC1 | CC3 | CC6,
+       .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2,
        .cst_limit = CST_LIMIT_HSW,
        .trl_msrs = TRL_BASE,
        .tcc_offset_bits = 6,
@@ -600,7 +600,7 @@ static const struct platform_features skx_features = {
        .has_nhm_msrs = 1,
        .has_config_tdp = 1,
        .bclk_freq = BCLK_100MHZ,
-       .supported_cstates = CC1 | CC3 | CC6,
+       .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2,
        .cst_limit = CST_LIMIT_SKX,
        .has_cst_auto_convension = 1,
        .trl_msrs = TRL_BASE | TRL_CORECOUNT,
@@ -614,7 +614,7 @@ static const struct platform_features icx_features = {
        .has_nhm_msrs = 1,
        .has_config_tdp = 1,
        .bclk_freq = BCLK_100MHZ,
-       .supported_cstates = CC1 | CC3 | CC6,
+       .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2,
        .cst_limit = CST_LIMIT_ICX,
        .trl_msrs = TRL_BASE | TRL_CORECOUNT,
        .rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL,
@@ -627,7 +627,7 @@ static const struct platform_features spr_features = {
        .has_nhm_msrs = 1,
        .has_config_tdp = 1,
        .bclk_freq = BCLK_100MHZ,
-       .supported_cstates = CC1 | CC3 | CC6,
+       .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2,
        .cst_limit = CST_LIMIT_SKX,
        .trl_msrs = TRL_BASE | TRL_CORECOUNT,
        .rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL,
@@ -668,7 +668,7 @@ static const struct platform_features gmt_features = {
        .has_nhm_msrs = 1,
        .bclk_freq = BCLK_100MHZ,
        .crystal_freq = 19200000,
-       .supported_cstates = CC1 | CC3 | CC6,
+       .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2,
        .cst_limit = CST_LIMIT_GMT,
        .trl_msrs = TRL_BASE | TRL_CORECOUNT,
        .rapl_msrs = RAPL_PKG | RAPL_PKG_POWER_INFO,
@@ -679,7 +679,7 @@ static const struct platform_features gmtd_features = {
        .has_nhm_msrs = 1,
        .bclk_freq = BCLK_100MHZ,
        .crystal_freq = 25000000,
-       .supported_cstates = CC1 | CC3 | CC6,
+       .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2,
        .cst_limit = CST_LIMIT_GMT,
        .trl_msrs = TRL_BASE | TRL_CORECOUNT,
        .rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL | RAPL_CORE_ENERGY_STATUS,
@@ -690,7 +690,7 @@ static const struct platform_features gmtp_features = {
        .has_nhm_msrs = 1,
        .bclk_freq = BCLK_100MHZ,
        .crystal_freq = 19200000,
-       .supported_cstates = CC1 | CC3 | CC6,
+       .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2,
        .cst_limit = CST_LIMIT_GMT,
        .trl_msrs = TRL_BASE,
        .rapl_msrs = RAPL_PKG | RAPL_PKG_POWER_INFO,
@@ -700,7 +700,7 @@ static const struct platform_features tmt_features = {
        .has_msr_misc_pwr_mgmt = 1,
        .has_nhm_msrs = 1,
        .bclk_freq = BCLK_100MHZ,
-       .supported_cstates = CC1 | CC3 | CC6,
+       .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2,
        .cst_limit = CST_LIMIT_GMT,
        .trl_msrs = TRL_BASE,
        .rapl_msrs = RAPL_PKG_ALL | RAPL_CORE_ALL | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_GFX,
@@ -711,7 +711,7 @@ static const struct platform_features tmtd_features = {
        .has_msr_misc_pwr_mgmt = 1,
        .has_nhm_msrs = 1,
        .bclk_freq = BCLK_100MHZ,
-       .supported_cstates = CC1 | CC3 | CC6,
+       .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2,
        .cst_limit = CST_LIMIT_GMT,
        .trl_msrs = TRL_BASE | TRL_CORECOUNT,
        .rapl_msrs = RAPL_PKG_ALL,
@@ -5829,12 +5829,7 @@ void process_cpuid()
        probe_bclk();
        do_snb_cstates = has_snb_msrs(family, model);
 
-       if (do_snb_cstates)
-               BIC_PRESENT(BIC_CPU_c7);
-
        do_irtl_snb = has_snb_msrs(family, model);
-       if (do_snb_cstates && (pkg_cstate_limit >= PCL__2))
-               BIC_PRESENT(BIC_Pkgpc2);
        if (pkg_cstate_limit >= PCL__3)
                BIC_PRESENT(BIC_Pkgpc3);
        if (pkg_cstate_limit >= PCL__6)