arm64: dts: qcom: Update cache properties

The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).

Update the Device Trees accordingly.

About msm8953.dtsi:
According to the Devicetree Specification v0.3,
s3.7.3 'Internal (L1) Cache Properties',
  cache-unified:
  If present, specifies the cache has a unified or-
  ganization. If not present, specifies that the
  cache has a Harvard architecture with separate
  caches for instructions and data.
Plus, the 'cache-level' property seems to be reserved to higher
cache levels (cf s3.8).

To describe a l1 data/instruction cache couple, no cache
information should be described. Remove the l1 cache nodes.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
[bjorn: Moved "qcom" to $subject prefix]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107155825.1644604-17-pierre.gondois@arm.com

diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi
index 62d2ae30711b3cd66c2eff9439b5aee842b842fb..091284756106db26af6aa0ea21ea05d3b56b6226 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8953.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi
@@ -42,13 +42,6 @@
                        capacity-dmips-mhz = <1024>;
                        next-level-cache = <&L2_0>;
                        #cooling-cells = <2>;
-
-                       l1-icache {
-                               compatible = "cache";
-                       };
-                       l1-dcache {
-                               compatible = "cache";
-                       };
                };
 
                CPU1: cpu@1 {
@@ -59,13 +52,6 @@
                        capacity-dmips-mhz = <1024>;
                        next-level-cache = <&L2_0>;
                        #cooling-cells = <2>;
-
-                       l1-icache {
-                               compatible = "cache";
-                       };
-                       l1-dcache {
-                               compatible = "cache";
-                       };
                };
 
                CPU2: cpu@2 {
@@ -76,13 +62,6 @@
                        capacity-dmips-mhz = <1024>;
                        next-level-cache = <&L2_0>;
                        #cooling-cells = <2>;
-
-                       l1-icache {
-                               compatible = "cache";
-                       };
-                       l1-dcache {
-                               compatible = "cache";
-                       };
                };
 
                CPU3: cpu@3 {
@@ -93,13 +72,6 @@
                        capacity-dmips-mhz = <1024>;
                        next-level-cache = <&L2_0>;
                        #cooling-cells = <2>;
-
-                       l1-icache {
-                               compatible = "cache";
-                       };
-                       l1-dcache {
-                               compatible = "cache";
-                       };
                };
 
                CPU4: cpu@100 {
@@ -110,13 +82,6 @@
                        capacity-dmips-mhz = <1024>;
                        next-level-cache = <&L2_1>;
                        #cooling-cells = <2>;
-
-                       l1-icache {
-                               compatible = "cache";
-                       };
-                       l1-dcache {
-                               compatible = "cache";
-                       };
                };
 
                CPU5: cpu@101 {
@@ -127,13 +92,6 @@
                        capacity-dmips-mhz = <1024>;
                        next-level-cache = <&L2_1>;
                        #cooling-cells = <2>;
-
-                       l1-icache {
-                               compatible = "cache";
-                       };
-                       l1-dcache {
-                               compatible = "cache";
-                       };
                };
 
                CPU6: cpu@102 {
@@ -144,13 +102,6 @@
                        capacity-dmips-mhz = <1024>;
                        next-level-cache = <&L2_1>;
                        #cooling-cells = <2>;
-
-                       l1-icache {
-                               compatible = "cache";
-                       };
-                       l1-dcache {
-                               compatible = "cache";
-                       };
                };
 
                CPU7: cpu@103 {
@@ -161,13 +112,6 @@
                        capacity-dmips-mhz = <1024>;
                        next-level-cache = <&L2_1>;
                        #cooling-cells = <2>;
-
-                       l1-icache {
-                               compatible = "cache";
-                       };
-                       l1-dcache {
-                               compatible = "cache";
-                       };
                };
 
                cpu-map {

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 773f182edc265d369bb4a0fc0021ac7bcf0806d0..b858091687f2c090dd60568f9483ce4ed2e01739 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -146,9 +146,11 @@
                        qcom,freq-domain = <&cpufreq_hw 0>;
                        L2_0: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                                L3_0: l3-cache {
                                        compatible = "cache";
+                                       cache-level = <3>;
                                };
                        };
                };
@@ -171,6 +173,7 @@
                        qcom,freq-domain = <&cpufreq_hw 0>;
                        L2_100: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -193,6 +196,7 @@
                        qcom,freq-domain = <&cpufreq_hw 0>;
                        L2_200: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -215,6 +219,7 @@
                        qcom,freq-domain = <&cpufreq_hw 0>;
                        L2_300: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -237,6 +242,7 @@
                        qcom,freq-domain = <&cpufreq_hw 0>;
                        L2_400: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -259,6 +265,7 @@
                        qcom,freq-domain = <&cpufreq_hw 0>;
                        L2_500: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -281,6 +288,7 @@
                        qcom,freq-domain = <&cpufreq_hw 1>;
                        L2_600: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -303,6 +311,7 @@
                        qcom,freq-domain = <&cpufreq_hw 1>;
                        L2_700: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 1fd2935ccd303e58932f63cf4ee68d8853e7c4ee..0388b3698e7010909ca4b1b37d8405d1484f7070 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -180,9 +180,11 @@
                        #cooling-cells = <2>;
                        L2_0: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                                L3_0: l3-cache {
                                        compatible = "cache";
+                                       cache-level = <3>;
                                };
                        };
                };
@@ -203,6 +205,7 @@
                        #cooling-cells = <2>;
                        L2_100: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -223,6 +226,7 @@
                        #cooling-cells = <2>;
                        L2_200: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -243,6 +247,7 @@
                        #cooling-cells = <2>;
                        L2_300: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -263,6 +268,7 @@
                        #cooling-cells = <2>;
                        L2_400: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -283,6 +289,7 @@
                        #cooling-cells = <2>;
                        L2_500: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -303,6 +310,7 @@
                        #cooling-cells = <2>;
                        L2_600: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -323,6 +331,7 @@
                        #cooling-cells = <2>;
                        L2_700: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index c6546d0d241ac61c541146995b7d282f947f0816..1f64a86beada4f77af31b30fd2c5e4e7f4ba2c2b 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -234,9 +234,11 @@
                        #cooling-cells = <2>;
                        L2_0: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                                L3_0: l3-cache {
                                      compatible = "cache";
+                                     cache-level = <3>;
                                };
                        };
                };
@@ -256,6 +258,7 @@
                        #cooling-cells = <2>;
                        L2_100: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -275,6 +278,7 @@
                        #cooling-cells = <2>;
                        L2_200: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -294,6 +298,7 @@
                        #cooling-cells = <2>;
                        L2_300: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -313,6 +318,7 @@
                        #cooling-cells = <2>;
                        L2_400: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -332,6 +338,7 @@
                        #cooling-cells = <2>;
                        L2_500: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -351,6 +358,7 @@
                        #cooling-cells = <2>;
                        L2_600: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -370,6 +378,7 @@
                        #cooling-cells = <2>;
                        L2_700: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 9d124610ec0c8cccae5e745a64367e9921e86d47..767486acbec8dc45ce7e0795b335e6f8f7406417 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -209,9 +209,11 @@
                        next-level-cache = <&L2_0>;
                        L2_0: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                                L3_0: l3-cache {
                                      compatible = "cache";
+                                     cache-level = <3>;
                                };
                        };
                };
@@ -233,6 +235,7 @@
                        next-level-cache = <&L2_100>;
                        L2_100: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -254,6 +257,7 @@
                        next-level-cache = <&L2_200>;
                        L2_200: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -275,6 +279,7 @@
                        next-level-cache = <&L2_300>;
                        L2_300: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -296,6 +301,7 @@
                        next-level-cache = <&L2_400>;
                        L2_400: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -317,6 +323,7 @@
                        next-level-cache = <&L2_500>;
                        L2_500: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -338,6 +345,7 @@
                        next-level-cache = <&L2_600>;
                        L2_600: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -359,6 +367,7 @@
                        next-level-cache = <&L2_700>;
                        L2_700: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };

diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index 7e25a4f85594f6d9a66d0f0bc55339dd97f67bfe..fa102ba4032b1e714a62df89b9b6ec02ce0d6fe7 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -45,6 +45,7 @@
                        next-level-cache = <&L2_0>;
                        L2_0: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                        };
                };
 
@@ -84,6 +85,7 @@
                        next-level-cache = <&L2_1>;
                        L2_1: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                        };
                };
 

diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 00e43a0d2dd67c8e78bd4ea01552cc070cfa77c3..dcf2e7ccaea717cc7ff39d7cedb467407c9ac2da 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -50,9 +50,11 @@
                        #cooling-cells = <2>;
                        L2_0: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                                L3_0: l3-cache {
                                        compatible = "cache";
+                                       cache-level = <3>;
                                };
                        };
                };
@@ -69,6 +71,7 @@
                        #cooling-cells = <2>;
                        L2_100: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -85,6 +88,7 @@
                        #cooling-cells = <2>;
                        L2_200: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -101,6 +105,7 @@
                        #cooling-cells = <2>;
                        L2_300: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -117,6 +122,7 @@
                        #cooling-cells = <2>;
                        L2_400: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -133,6 +139,7 @@
                        #cooling-cells = <2>;
                        L2_500: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
 
@@ -150,6 +157,7 @@
                        #cooling-cells = <2>;
                        L2_600: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -166,6 +174,7 @@
                        #cooling-cells = <2>;
                        L2_700: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };

diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index c13acede4594760a56eedb149ced3a4ab1c09b64..70d436dd158abac778d5cf58f738e6f5fb162574 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -60,9 +60,11 @@
                        #cooling-cells = <2>;
                        L2_0: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                                L3_0: l3-cache {
                                      compatible = "cache";
+                                     cache-level = <3>;
                                };
                        };
                };
@@ -84,6 +86,7 @@
                        #cooling-cells = <2>;
                        L2_100: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
 
@@ -106,6 +109,7 @@
                        #cooling-cells = <2>;
                        L2_200: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -127,6 +131,7 @@
                        #cooling-cells = <2>;
                        L2_300: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -148,6 +153,7 @@
                        #cooling-cells = <2>;
                        L2_400: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -169,6 +175,7 @@
                        #cooling-cells = <2>;
                        L2_500: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -190,6 +197,7 @@
                        #cooling-cells = <2>;
                        L2_600: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -211,6 +219,7 @@
                        #cooling-cells = <2>;
                        L2_700: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 1e4a281602e10b708db93a54a65b572420ee9439..2baaa63737053d55ff16142645542425bc87537d 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -110,9 +110,11 @@
                        #cooling-cells = <2>;
                        L2_0: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                                L3_0: l3-cache {
                                        compatible = "cache";
+                                       cache-level = <3>;
                                };
                        };
                };
@@ -134,6 +136,7 @@
                        #cooling-cells = <2>;
                        L2_100: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -155,6 +158,7 @@
                        #cooling-cells = <2>;
                        L2_200: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -176,6 +180,7 @@
                        #cooling-cells = <2>;
                        L2_300: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -197,6 +202,7 @@
                        #cooling-cells = <2>;
                        L2_400: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -218,6 +224,7 @@
                        #cooling-cells = <2>;
                        L2_500: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
 
@@ -240,6 +247,7 @@
                        #cooling-cells = <2>;
                        L2_600: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };
@@ -261,6 +269,7 @@
                        #cooling-cells = <2>;
                        L2_700: l2-cache {
                                compatible = "cache";
+                               cache-level = <2>;
                                next-level-cache = <&L3_0>;
                        };
                };

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 245dce24ec599c0d8b062f9953a234a792508616..2eccf14a9a312b5ef979d2953d624e5e52337cb1 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -73,9 +73,11 @@
                        #cooling-cells = <2>;
                        L2_0: l2-cache {
                              compatible = "cache";
+                             cache-level = <2>;
                              next-level-cache = <&L3_0>;
                                L3_0: l3-cache {
                                      compatible = "cache";
+                                     cache-level = <3>;
                                };
                        };
                };
@@ -92,6 +94,7 @@
                        #cooling-cells = <2>;
                        L2_100: l2-cache {
                              compatible = "cache";
+                             cache-level = <2>;
                              next-level-cache = <&L3_0>;
                        };
                };
@@ -108,6 +111,7 @@
                        #cooling-cells = <2>;
                        L2_200: l2-cache {
                              compatible = "cache";
+                             cache-level = <2>;
                              next-level-cache = <&L3_0>;
                        };
                };
@@ -124,6 +128,7 @@
                        #cooling-cells = <2>;
                        L2_300: l2-cache {
                              compatible = "cache";
+                             cache-level = <2>;
                              next-level-cache = <&L3_0>;
                        };
                };
@@ -140,6 +145,7 @@
                        #cooling-cells = <2>;
                        L2_400: l2-cache {
                              compatible = "cache";
+                             cache-level = <2>;
                              next-level-cache = <&L3_0>;
                        };
                };
@@ -156,6 +162,7 @@
                        #cooling-cells = <2>;
                        L2_500: l2-cache {
                              compatible = "cache";
+                             cache-level = <2>;
                              next-level-cache = <&L3_0>;
                        };
 
@@ -173,6 +180,7 @@
                        #cooling-cells = <2>;
                        L2_600: l2-cache {
                              compatible = "cache";
+                             cache-level = <2>;
                              next-level-cache = <&L3_0>;
                        };
                };
@@ -189,6 +197,7 @@
                        #cooling-cells = <2>;
                        L2_700: l2-cache {
                              compatible = "cache";
+                             cache-level = <2>;
                              next-level-cache = <&L3_0>;
                        };
                };

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index e9e51b1a1bd30dedc0cd6cee836c79a904fa6227..1610f5ea49d2db471a3aaac10ad66df6cd3f339d 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -57,9 +57,11 @@
                        clocks = <&cpufreq_hw 0>;
                        L2_0: l2-cache {
                              compatible = "cache";
+                             cache-level = <2>;
                              next-level-cache = <&L3_0>;
                                L3_0: l3-cache {
                                      compatible = "cache";
+                                     cache-level = <3>;
                                };
                        };
                };
@@ -77,6 +79,7 @@
                        clocks = <&cpufreq_hw 0>;
                        L2_100: l2-cache {
                              compatible = "cache";
+                             cache-level = <2>;
                              next-level-cache = <&L3_0>;
                        };
                };
@@ -94,6 +97,7 @@
                        clocks = <&cpufreq_hw 0>;
                        L2_200: l2-cache {
                              compatible = "cache";
+                             cache-level = <2>;
                              next-level-cache = <&L3_0>;
                        };
                };
@@ -111,6 +115,7 @@
                        clocks = <&cpufreq_hw 0>;
                        L2_300: l2-cache {
                              compatible = "cache";
+                             cache-level = <2>;
                              next-level-cache = <&L3_0>;
                        };
                };
@@ -128,6 +133,7 @@
                        clocks = <&cpufreq_hw 1>;
                        L2_400: l2-cache {
                              compatible = "cache";
+                             cache-level = <2>;
                              next-level-cache = <&L3_0>;
                        };
                };
@@ -145,6 +151,7 @@
                        clocks = <&cpufreq_hw 1>;
                        L2_500: l2-cache {
                              compatible = "cache";
+                             cache-level = <2>;
                              next-level-cache = <&L3_0>;
                        };
 
@@ -163,6 +170,7 @@
                        clocks = <&cpufreq_hw 1>;
                        L2_600: l2-cache {
                              compatible = "cache";
+                             cache-level = <2>;
                              next-level-cache = <&L3_0>;
                        };
                };
@@ -180,6 +188,7 @@
                        clocks = <&cpufreq_hw 2>;
                        L2_700: l2-cache {
                              compatible = "cache";
+                             cache-level = <2>;
                              next-level-cache = <&L3_0>;
                        };
                };