media: ccs-pll: Use correct VT divisor for calculating VT SYS divisor

Use the correct video timing divisor to calculate the SYS divisor. Instead
of the current value, the minimum was used. This could have resulted in a
too low SYS divisor.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index b2f0fa14ff9202c7c6c5892bd9273976ba026347..ea0f84fc8a90442b81a55dca6333a3b71b392427 100644 (file)
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -365,14 +365,14 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
 
                        /* Check if this one is better. */
                        if (pix_div * sys_div
-                           <= roundup(min_vt_div, best_pix_div))
+                           <= roundup(vt_div, best_pix_div))
                                best_pix_div = pix_div;
                }
                if (best_pix_div < INT_MAX >> 1)
                        break;
        }
 
-       pll->vt_bk.sys_clk_div = DIV_ROUND_UP(min_vt_div, best_pix_div);
+       pll->vt_bk.sys_clk_div = DIV_ROUND_UP(vt_div, best_pix_div);
        pll->vt_bk.pix_clk_div = best_pix_div;
 
        pll->vt_bk.sys_clk_freq_hz =