mmc: sdhci-pci-gli: Use PCI AER definitions, not hard-coded values

015c9cbcf0ad ("mmc: sdhci-pci-gli: GL9750: Mask the replay timer timeout of
AER") added PCI_GLI_9750_CORRERR_MASK, the offset of the AER Capability in
config space, and PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT, the
Replay Timer Timeout bit in the AER Correctable Error Status register.

Use pci_find_ext_capability() to locate the AER Capability and use the
existing PCI_ERR_COR_REP_TIMER definition to mask the bit.

This removes a little bit of unnecessarily device-specific code and makes
AER-related things more greppable.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20240327214831.1544595-2-helgaas@kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
index 77911a57b12cfc5ceafbf28447fea83e109017a0..3d554358153787e19c05090698ea63e06d572b2b 100644 (file)
--- a/drivers/mmc/host/sdhci-pci-gli.c
+++ b/drivers/mmc/host/sdhci-pci-gli.c
@@ -28,9 +28,6 @@
 #define PCI_GLI_9750_PM_CTRL   0xFC
 #define   PCI_GLI_9750_PM_STATE          GENMASK(1, 0)
 
-#define PCI_GLI_9750_CORRERR_MASK                              0x214
-#define   PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT         BIT(12)
-
 #define SDHCI_GLI_9750_CFG2          0x848
 #define   SDHCI_GLI_9750_CFG2_L1DLY    GENMASK(28, 24)
 #define   GLI_9750_CFG2_L1DLY_VALUE    0x1F
@@ -155,9 +152,6 @@
 #define PCI_GLI_9755_PM_CTRL     0xFC
 #define   PCI_GLI_9755_PM_STATE    GENMASK(1, 0)
 
-#define PCI_GLI_9755_CORRERR_MASK                              0x214
-#define   PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT         BIT(12)
-
 #define SDHCI_GLI_9767_GM_BURST_SIZE                   0x510
 #define   SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET    BIT(8)
 
@@ -547,6 +541,7 @@ static void gl9750_hw_setting(struct sdhci_host *host)
 {
        struct sdhci_pci_slot *slot = sdhci_priv(host);
        struct pci_dev *pdev;
+       int aer;
        u32 value;
 
        pdev = slot->chip->pdev;
@@ -568,9 +563,12 @@ static void gl9750_hw_setting(struct sdhci_host *host)
        pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value);
 
        /* mask the replay timer timeout of AER */
-       pci_read_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, &value);
-       value |= PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT;
-       pci_write_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, value);
+       aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
+       if (aer) {
+               pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value);
+               value |= PCI_ERR_COR_REP_TIMER;
+               pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value);
+       }
 
        gl9750_wt_off(host);
 }
@@ -745,6 +743,7 @@ static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock)
 static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
 {
        struct pci_dev *pdev = slot->chip->pdev;
+       int aer;
        u32 value;
 
        gl9755_wt_on(pdev);
@@ -782,9 +781,12 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
        pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
 
        /* mask the replay timer timeout of AER */
-       pci_read_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, &value);
-       value |= PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT;
-       pci_write_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, value);
+       aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
+       if (aer) {
+               pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value);
+               value |= PCI_ERR_COR_REP_TIMER;
+               pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value);
+       }
 
        gl9755_wt_off(pdev);
 }