irqchip/sifive-plic: Parse number of interrupts and contexts early in plic_probe()
authorAnup Patel <apatel@ventanamicro.com>
Thu, 22 Feb 2024 09:39:54 +0000 (15:09 +0530)
committerThomas Gleixner <tglx@linutronix.de>
Fri, 23 Feb 2024 09:18:44 +0000 (10:18 +0100)
The SiFive PLIC driver needs to know the number of interrupts and contexts
to complete initialization. Parse these details early in plic_probe() to
avoid unnecessary memory allocations and register mappings if these details
are not available.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20240222094006.1030709-7-apatel@ventanamicro.com
drivers/irqchip/irq-sifive-plic.c

index a399cb3f44af55d029060417d87914d04791dfaf..474ddc33a54a497a01b9d64b734d1d034055241b 100644 (file)
@@ -417,6 +417,34 @@ static const struct of_device_id plic_match[] = {
        {}
 };
 
+static int plic_parse_nr_irqs_and_contexts(struct platform_device *pdev,
+                                          u32 *nr_irqs, u32 *nr_contexts)
+{
+       struct device *dev = &pdev->dev;
+       int rc;
+
+       /*
+        * Currently, only OF fwnode is supported so extend this
+        * function for ACPI support.
+        */
+       if (!is_of_node(dev->fwnode))
+               return -EINVAL;
+
+       rc = of_property_read_u32(to_of_node(dev->fwnode), "riscv,ndev", nr_irqs);
+       if (rc) {
+               dev_err(dev, "riscv,ndev property not available\n");
+               return rc;
+       }
+
+       *nr_contexts = of_irq_count(to_of_node(dev->fwnode));
+       if (WARN_ON(!(*nr_contexts))) {
+               dev_err(dev, "no PLIC context available\n");
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
 static int plic_parse_context_parent(struct platform_device *pdev, u32 context,
                                     u32 *parent_hwirq, int *parent_cpu)
 {
@@ -465,31 +493,26 @@ static int plic_probe(struct platform_device *pdev)
                        plic_quirks = (unsigned long)id->data;
        }
 
+       error = plic_parse_nr_irqs_and_contexts(pdev, &nr_irqs, &nr_contexts);
+       if (error)
+               return error;
+
        priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
        if (!priv)
                return -ENOMEM;
 
        priv->dev = dev;
        priv->plic_quirks = plic_quirks;
+       priv->nr_irqs = nr_irqs;
 
        priv->regs = devm_platform_ioremap_resource(pdev, 0);
        if (WARN_ON(!priv->regs))
                return -EIO;
 
-       of_property_read_u32(to_of_node(dev->fwnode), "riscv,ndev", &nr_irqs);
-       if (WARN_ON(!nr_irqs))
-               return -EINVAL;
-
-       priv->nr_irqs = nr_irqs;
-
        priv->prio_save = devm_bitmap_zalloc(dev, nr_irqs, GFP_KERNEL);
        if (!priv->prio_save)
                return -ENOMEM;
 
-       nr_contexts = of_irq_count(to_of_node(dev->fwnode));
-       if (WARN_ON(!nr_contexts))
-               return -EINVAL;
-
        for (i = 0; i < nr_contexts; i++) {
                error = plic_parse_context_parent(pdev, i, &parent_hwirq, &cpu);
                if (error) {