ARM: dts: s5pv210: Adjust memory reg entries to match spec
authorJonathan Bakker <xc-racer2@live.ca>
Sun, 27 Mar 2022 18:08:52 +0000 (11:08 -0700)
committerKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Sat, 9 Apr 2022 16:50:05 +0000 (18:50 +0200)
The reg property of memory nodes should have pairs of offset, size;
not all memory banks lumped in as one.

Signed-off-by: Jonathan Bakker <xc-racer2@live.ca>
Link: https://lore.kernel.org/r/CY4PR04MB05677849A13F41BF603906DFCB1C9@CY4PR04MB0567.namprd04.prod.outlook.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
arch/arm/boot/dts/s5pv210-aquila.dts
arch/arm/boot/dts/s5pv210-aries.dtsi
arch/arm/boot/dts/s5pv210-goni.dts

index 54de3bc77c3083ba870a5ecb0a7566d873f48b15..bc0b7354b6c0604e3a6352b6b5ff0b20df9a66db 100644 (file)
@@ -29,8 +29,7 @@
 
        memory@30000000 {
                device_type = "memory";
-               reg = <0x30000000 0x05000000
-                       0x40000000 0x18000000>;
+               reg = <0x30000000 0x05000000>, <0x40000000 0x18000000>;
        };
 
        pmic_ap_clk: clock-0 {
index 9ae4c4a0fab87cdccb34243f4f67c184d7f7d604..32216aa542b22cb27e9633ce294fe65dc63cc429 100644 (file)
@@ -24,9 +24,9 @@
 
        memory@30000000 {
                device_type = "memory";
-               reg = <0x30000000 0x05000000
-                       0x40000000 0x10000000
-                       0x50000000 0x08000000>;
+               reg = <0x30000000 0x05000000>,
+                       <0x40000000 0x10000000>,
+                       <0x50000000 0x08000000>;
        };
 
        reserved-memory {
index c6f39147cb960004953f998b50f53521e0c67dd0..d32f42dd1bf56efc9d24d3ca7f1e41219472ae34 100644 (file)
@@ -30,9 +30,9 @@
 
        memory@30000000 {
                device_type = "memory";
-               reg = <0x30000000 0x05000000
-                       0x40000000 0x10000000
-                       0x50000000 0x08000000>;
+               reg = <0x30000000 0x05000000>,
+                       <0x40000000 0x10000000>,
+                       <0x50000000 0x08000000>;
        };
 
        pmic_ap_clk: clock-0 {