irqchip/riscv-intc: Allow large non-standard interrupt number

Currently, the implementation of the RISC-V INTC driver uses the
interrupt cause as the hardware interrupt number, with a maximum of
64 interrupts. However, the platform can expand the interrupt number
further for custom local interrupts.

To fully utilize the available local interrupt sources, switch
to using irq_domain_create_tree() that creates the radix tree
map, add global variables (riscv_intc_nr_irqs, riscv_intc_custom_base
and riscv_intc_custom_nr_irqs) to determine the valid range of local
interrupt number (hwirq).

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Randolph <randolph@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20240222083946.3977135-3-peterlin@andestech.com

diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index e8d01b14ccdde7848c7fb14489a5a015b86e8e95..684875c39728058a805ee7cbec7e8f1bdfa03048 100644 (file)
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -19,15 +19,16 @@
 #include <linux/smp.h>
 
 static struct irq_domain *intc_domain;
+static unsigned int riscv_intc_nr_irqs __ro_after_init = BITS_PER_LONG;
+static unsigned int riscv_intc_custom_base __ro_after_init = BITS_PER_LONG;
+static unsigned int riscv_intc_custom_nr_irqs __ro_after_init;
 
 static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
 {
        unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
 
-       if (unlikely(cause >= BITS_PER_LONG))
-               panic("unexpected interrupt cause");
-
-       generic_handle_domain_irq(intc_domain, cause);
+       if (generic_handle_domain_irq(intc_domain, cause))
+               pr_warn_ratelimited("Failed to handle interrupt (cause: %ld)\n", cause);
 }
 
 /*
@@ -93,6 +94,14 @@ static int riscv_intc_domain_alloc(struct irq_domain *domain,
        if (ret)
                return ret;
 
+       /*
+        * Only allow hwirq for which we have corresponding standard or
+        * custom interrupt enable register.
+        */
+       if ((hwirq >= riscv_intc_nr_irqs && hwirq < riscv_intc_custom_base) ||
+           (hwirq >= riscv_intc_custom_base + riscv_intc_custom_nr_irqs))
+               return -EINVAL;
+
        for (i = 0; i < nr_irqs; i++) {
                ret = riscv_intc_domain_map(domain, virq + i, hwirq + i);
                if (ret)
@@ -117,8 +126,7 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
 {
        int rc;
 
-       intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG,
-                                              &riscv_intc_domain_ops, NULL);
+       intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL);
        if (!intc_domain) {
                pr_err("unable to add IRQ domain\n");
                return -ENXIO;
@@ -132,7 +140,11 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
 
        riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
 
-       pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
+       pr_info("%d local interrupts mapped\n", riscv_intc_nr_irqs);
+       if (riscv_intc_custom_nr_irqs) {
+               pr_info("%d custom local interrupts mapped\n",
+                       riscv_intc_custom_nr_irqs);
+       }
 
        return 0;
 }