drm/amdgpu: add PSP FW TYPE for VPE
authorLang Yu <Lang.Yu@amd.com>
Sat, 6 May 2023 02:09:32 +0000 (10:09 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 31 Aug 2023 20:33:50 +0000 (16:33 -0400)
Add PSP FW TYPE for Video Processing Engine.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h

index 429ef212c1f25b4865953083ef32196f0e3628a6..46295c8c45571ab4d2907ad1a6c3186bfd9ee92c 100644 (file)
@@ -2390,6 +2390,12 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
        case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
                *type = GFX_FW_TYPE_RS64_MEC_P3_STACK;
                break;
+       case AMDGPU_UCODE_ID_VPE_CTX:
+               *type = GFX_FW_TYPE_VPEC_FW1;
+               break;
+       case AMDGPU_UCODE_ID_VPE_CTL:
+               *type = GFX_FW_TYPE_VPEC_FW2;
+               break;
        case AMDGPU_UCODE_ID_MAXIMUM:
        default:
                return -EINVAL;
index 18917df785ecafc76e08dc99a78973be53df220c..fd11115429c861232318389dda0cdc4422aa9bbd 100644 (file)
@@ -293,6 +293,8 @@ enum psp_gfx_fw_type {
        GFX_FW_TYPE_RS64_MEC_P1_STACK               = 95,   /* RS64 MEC stack P1        SOC21   */
        GFX_FW_TYPE_RS64_MEC_P2_STACK               = 96,   /* RS64 MEC stack P2        SOC21   */
        GFX_FW_TYPE_RS64_MEC_P3_STACK               = 97,   /* RS64 MEC stack P3        SOC21   */
+       GFX_FW_TYPE_VPEC_FW1                        = 100,  /* VPEC FW1 To Save         VPE     */
+       GFX_FW_TYPE_VPEC_FW2                        = 101,  /* VPEC FW2 To Save         VPE     */
        GFX_FW_TYPE_MAX
 };