drm/amdgpu/sienna_cichlid_ppt: convert to IP version checking

Use IP versions rather than asic_type to differentiate
IP version specific features.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index ca57221e39629c68c9c62b836131edbd149058b6..6a0fed5e33d9509f762a6f16789624de813d717e 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -74,7 +74,7 @@
 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
 
 #define GET_PPTABLE_MEMBER(field, member) do {\
-       if (smu->adev->asic_type == CHIP_BEIGE_GOBY)\
+       if (smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))\
                (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
        else\
                (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
@@ -82,7 +82,7 @@
 
 static int get_table_size(struct smu_context *smu)
 {
-       if (smu->adev->asic_type == CHIP_BEIGE_GOBY)
+       if (smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))
                return sizeof(PPTable_beige_goby_t);
        else
                return sizeof(PPTable_t);
@@ -298,7 +298,7 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
        }
 
        if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
-           (adev->asic_type > CHIP_SIENNA_CICHLID) &&
+           (adev->ip_versions[MP1_HWIP] > IP_VERSION(11, 0, 7)) &&
            !(adev->flags & AMD_IS_APU))
                *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
 
@@ -496,7 +496,7 @@ static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *s
        uint32_t throttler_status = 0;
        int i;
 
-       if ((smu->adev->asic_type == CHIP_SIENNA_CICHLID) &&
+       if ((smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
             (smu->smc_fw_version >= 0x3A4300)) {
                for (i = 0; i < THROTTLER_COUNT; i++)
                        throttler_status |=
@@ -517,7 +517,7 @@ static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
                &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
        SmuMetrics_V2_t *metrics_v2 =
                &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
-       bool use_metrics_v2 = ((smu->adev->asic_type == CHIP_SIENNA_CICHLID) &&
+       bool use_metrics_v2 = ((smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
                (smu->smc_fw_version >= 0x3A4300)) ? true : false;
        uint16_t average_gfx_activity;
        int ret = 0;
@@ -1170,7 +1170,7 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
                 * and onwards SMU firmwares.
                 */
                smu_cmn_get_smc_version(smu, NULL, &smu_version);
-               if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
+               if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
                     (smu_version < 0x003a2900))
                        break;
 
@@ -1937,7 +1937,7 @@ static void sienna_cichlid_dump_od_table(struct smu_context *smu,
                                                        od_table->UclkFmax);
 
        smu_cmn_get_smc_version(smu, NULL, &smu_version);
-       if (!((adev->asic_type == CHIP_SIENNA_CICHLID) &&
+       if (!((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
               (smu_version < 0x003a2900)))
                dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
 }
@@ -2161,7 +2161,7 @@ static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
                 * and onwards SMU firmwares.
                 */
                smu_cmn_get_smc_version(smu, NULL, &smu_version);
-               if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
+               if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
                     (smu_version < 0x003a2900)) {
                        dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
                                                "only by 58.41.0 and onwards SMU firmwares!\n");
@@ -2865,7 +2865,7 @@ static void sienna_cichlid_dump_pptable(struct smu_context *smu)
        PPTable_t *pptable = table_context->driver_pptable;
        int i;
 
-       if (smu->adev->asic_type == CHIP_BEIGE_GOBY) {
+       if (smu->adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13)) {
                beige_goby_dump_pptable(smu);
                return;
        }
@@ -3625,7 +3625,7 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
        SmuMetrics_V2_t *metrics_v2 =
                &(metrics_external.SmuMetrics_V2);
        struct amdgpu_device *adev = smu->adev;
-       bool use_metrics_v2 = ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
+       bool use_metrics_v2 = ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) &&
                (smu->smc_fw_version >= 0x3A4300)) ? true : false;
        uint16_t average_gfx_activity;
        int ret = 0;
@@ -3706,8 +3706,8 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
 
        gpu_metrics->current_fan_speed = use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
 
-       if (((adev->asic_type == CHIP_SIENNA_CICHLID) && smu->smc_fw_version > 0x003A1E00) ||
-             ((adev->asic_type == CHIP_NAVY_FLOUNDER) && smu->smc_fw_version > 0x00410400)) {
+       if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) ||
+             ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) {
                gpu_metrics->pcie_link_width = use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
                gpu_metrics->pcie_link_speed = link_speed[use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
        } else {