riscv: dts: add initial Sophgo SG2042 SoC device tree

Milk-V Pioneer motherboard is powered by SG2042.

SG2042 is server grade chip with high performance, low power
consumption and high data throughput.
Key features:
- 64 RISC-V cpu cores
- 4 cores per cluster, 16 clusters on chip
- More info is available at [1].

Currently only support booting into console with only uart,
other features will be added soon later.

Link: https://en.sophgo.com/product/introduce/sg2042.html
Reviewed-by: Guo Ren <guoren@kernel.org>
Acked-by: Chao Wei <chao.wei@sophgo.com>
Co-developed-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
Co-developed-by: Inochi Amaoto <inochiama@outlook.com>
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/MAINTAINERS b/MAINTAINERS
index 97cb8abcfeeee0ec75a9812e52e73b0773beb444..fedf042e5fb4fff9277e568bea3205b8bb06cd15 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20067,6 +20067,7 @@ SOPHGO DEVICETREES
 M:     Chao Wei <chao.wei@sophgo.com>
 M:     Chen Wang <unicorn_wang@outlook.com>
 S:     Maintained
+F:     arch/riscv/boot/dts/sophgo/
 F:     Documentation/devicetree/bindings/riscv/sophgo.yaml
 
 SOUND

diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
new file mode 100644 (file)
index 0000000..b136b6c
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
@@ -0,0 +1,2000 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
+ */
+
+/ {
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               timebase-frequency = <50000000>;
+
+               cpu-map {
+                       socket0 {
+                               cluster0 {
+                                        core0 {
+                                               cpu = <&cpu0>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu1>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu2>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu3>;
+                                        };
+                               };
+
+                               cluster1 {
+                                        core0 {
+                                               cpu = <&cpu4>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu5>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu6>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu7>;
+                                        };
+                               };
+
+                               cluster2 {
+                                        core0 {
+                                               cpu = <&cpu16>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu17>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu18>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu19>;
+                                        };
+                               };
+
+                               cluster3 {
+                                        core0 {
+                                               cpu = <&cpu20>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu21>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu22>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu23>;
+                                        };
+                               };
+
+                               cluster4 {
+                                        core0 {
+                                               cpu = <&cpu8>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu9>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu10>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu11>;
+                                        };
+                               };
+
+                               cluster5 {
+                                        core0 {
+                                               cpu = <&cpu12>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu13>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu14>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu15>;
+                                        };
+                               };
+
+                               cluster6 {
+                                        core0 {
+                                               cpu = <&cpu24>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu25>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu26>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu27>;
+                                        };
+                               };
+
+                               cluster7 {
+                                        core0 {
+                                               cpu = <&cpu28>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu29>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu30>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu31>;
+                                        };
+                               };
+
+                               cluster8 {
+                                        core0 {
+                                               cpu = <&cpu32>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu33>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu34>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu35>;
+                                        };
+                               };
+
+                               cluster9 {
+                                        core0 {
+                                               cpu = <&cpu36>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu37>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu38>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu39>;
+                                        };
+                               };
+
+                               cluster10 {
+                                        core0 {
+                                               cpu = <&cpu48>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu49>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu50>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu51>;
+                                        };
+                               };
+
+                               cluster11 {
+                                        core0 {
+                                               cpu = <&cpu52>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu53>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu54>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu55>;
+                                        };
+                               };
+
+                               cluster12 {
+                                        core0 {
+                                               cpu = <&cpu40>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu41>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu42>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu43>;
+                                        };
+                               };
+
+                               cluster13 {
+                                        core0 {
+                                               cpu = <&cpu44>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu45>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu46>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu47>;
+                                        };
+                               };
+
+                               cluster14 {
+                                        core0 {
+                                               cpu = <&cpu56>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu57>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu58>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu59>;
+                                        };
+                               };
+
+                               cluster15 {
+                                        core0 {
+                                               cpu = <&cpu60>;
+                                        };
+                                        core1 {
+                                               cpu = <&cpu61>;
+                                        };
+                                        core2 {
+                                               cpu = <&cpu62>;
+                                        };
+                                        core3 {
+                                               cpu = <&cpu63>;
+                                        };
+                               };
+                       };
+               };
+
+               cpu0: cpu@0 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <0>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache0>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu0_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu1: cpu@1 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <1>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache0>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu1_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu2: cpu@2 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <2>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache0>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu2_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu3: cpu@3 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <3>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache0>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu3_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu4: cpu@4 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <4>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache1>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu4_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu5: cpu@5 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <5>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache1>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu5_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu6: cpu@6 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <6>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache1>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu6_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu7: cpu@7 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <7>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache1>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu7_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu8: cpu@8 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <8>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache4>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu8_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu9: cpu@9 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <9>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache4>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu9_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu10: cpu@10 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <10>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache4>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu10_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu11: cpu@11 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <11>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache4>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu11_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu12: cpu@12 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <12>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache5>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu12_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu13: cpu@13 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <13>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache5>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu13_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu14: cpu@14 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <14>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache5>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu14_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu15: cpu@15 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <15>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache5>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu15_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu16: cpu@16 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <16>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache2>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu16_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu17: cpu@17 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <17>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache2>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu17_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu18: cpu@18 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <18>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache2>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu18_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu19: cpu@19 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <19>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache2>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu19_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu20: cpu@20 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <20>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache3>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu20_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu21: cpu@21 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <21>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache3>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu21_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu22: cpu@22 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <22>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache3>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu22_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu23: cpu@23 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <23>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache3>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu23_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu24: cpu@24 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <24>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache6>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu24_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu25: cpu@25 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <25>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache6>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu25_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu26: cpu@26 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <26>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache6>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu26_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu27: cpu@27 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <27>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache6>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu27_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu28: cpu@28 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <28>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache7>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu28_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu29: cpu@29 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <29>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache7>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu29_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu30: cpu@30 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <30>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache7>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu30_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu31: cpu@31 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <31>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache7>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu31_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu32: cpu@32 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <32>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache8>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu32_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu33: cpu@33 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <33>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache8>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu33_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu34: cpu@34 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <34>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache8>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu34_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu35: cpu@35 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <35>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache8>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu35_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu36: cpu@36 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <36>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache9>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu36_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu37: cpu@37 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <37>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache9>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu37_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu38: cpu@38 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <38>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache9>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu38_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu39: cpu@39 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <39>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache9>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu39_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu40: cpu@40 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <40>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache12>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu40_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu41: cpu@41 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <41>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache12>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu41_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu42: cpu@42 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <42>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache12>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu42_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu43: cpu@43 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <43>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache12>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu43_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu44: cpu@44 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <44>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache13>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu44_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu45: cpu@45 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <45>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache13>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu45_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu46: cpu@46 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <46>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache13>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu46_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu47: cpu@47 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <47>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache13>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu47_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu48: cpu@48 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <48>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache10>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu48_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu49: cpu@49 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <49>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache10>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu49_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu50: cpu@50 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <50>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache10>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu50_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu51: cpu@51 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <51>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache10>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu51_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu52: cpu@52 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <52>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache11>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu52_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu53: cpu@53 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <53>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache11>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu53_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu54: cpu@54 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <54>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache11>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu54_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu55: cpu@55 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <55>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache11>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu55_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu56: cpu@56 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <56>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache14>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu56_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu57: cpu@57 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <57>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache14>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu57_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu58: cpu@58 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <58>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache14>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu58_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu59: cpu@59 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <59>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache14>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu59_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu60: cpu@60 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <60>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache15>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu60_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu61: cpu@61 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <61>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache15>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu61_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu62: cpu@62 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <62>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache15>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu62_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               cpu63: cpu@63 {
+                       compatible = "thead,c920", "riscv";
+                       device_type = "cpu";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+                                              "zicntr", "zicsr", "zifencei",
+                                              "zihpm";
+                       reg = <63>;
+                       i-cache-block-size = <64>;
+                       i-cache-size = <65536>;
+                       i-cache-sets = <512>;
+                       d-cache-block-size = <64>;
+                       d-cache-size = <65536>;
+                       d-cache-sets = <512>;
+                       next-level-cache = <&l2_cache15>;
+                       mmu-type = "riscv,sv39";
+
+                       cpu63_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               l2_cache0: cache-controller-0 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache1: cache-controller-1 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache2: cache-controller-2 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache3: cache-controller-3 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache4: cache-controller-4 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache5: cache-controller-5 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache6: cache-controller-6 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache7: cache-controller-7 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache8: cache-controller-8 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache9: cache-controller-9 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache10: cache-controller-10 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache11: cache-controller-11 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache12: cache-controller-12 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache13: cache-controller-13 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache14: cache-controller-14 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+
+               l2_cache15: cache-controller-15 {
+                       compatible = "cache";
+                       cache-block-size = <64>;
+                       cache-level = <2>;
+                       cache-size = <1048576>;
+                       cache-sets = <1024>;
+                       cache-unified;
+               };
+       };
+};

diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
new file mode 100644 (file)
index 0000000..9325654
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -0,0 +1,325 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
+ */
+
+/dts-v1/;
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "sg2042-cpus.dtsi"
+
+/ {
+       compatible = "sophgo,sg2042";
+       #address-cells = <2>;
+       #size-cells = <2>;
+       dma-noncoherent;
+
+       aliases {
+               serial0 = &uart0;
+       };
+
+       soc: soc {
+               compatible = "simple-bus";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               clint_mswi: interrupt-controller@7094000000 {
+                       compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
+                       reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
+                       interrupts-extended = <&cpu0_intc 3>,
+                                             <&cpu1_intc 3>,
+                                             <&cpu2_intc 3>,
+                                             <&cpu3_intc 3>,
+                                             <&cpu4_intc 3>,
+                                             <&cpu5_intc 3>,
+                                             <&cpu6_intc 3>,
+                                             <&cpu7_intc 3>,
+                                             <&cpu8_intc 3>,
+                                             <&cpu9_intc 3>,
+                                             <&cpu10_intc 3>,
+                                             <&cpu11_intc 3>,
+                                             <&cpu12_intc 3>,
+                                             <&cpu13_intc 3>,
+                                             <&cpu14_intc 3>,
+                                             <&cpu15_intc 3>,
+                                             <&cpu16_intc 3>,
+                                             <&cpu17_intc 3>,
+                                             <&cpu18_intc 3>,
+                                             <&cpu19_intc 3>,
+                                             <&cpu20_intc 3>,
+                                             <&cpu21_intc 3>,
+                                             <&cpu22_intc 3>,
+                                             <&cpu23_intc 3>,
+                                             <&cpu24_intc 3>,
+                                             <&cpu25_intc 3>,
+                                             <&cpu26_intc 3>,
+                                             <&cpu27_intc 3>,
+                                             <&cpu28_intc 3>,
+                                             <&cpu29_intc 3>,
+                                             <&cpu30_intc 3>,
+                                             <&cpu31_intc 3>,
+                                             <&cpu32_intc 3>,
+                                             <&cpu33_intc 3>,
+                                             <&cpu34_intc 3>,
+                                             <&cpu35_intc 3>,
+                                             <&cpu36_intc 3>,
+                                             <&cpu37_intc 3>,
+                                             <&cpu38_intc 3>,
+                                             <&cpu39_intc 3>,
+                                             <&cpu40_intc 3>,
+                                             <&cpu41_intc 3>,
+                                             <&cpu42_intc 3>,
+                                             <&cpu43_intc 3>,
+                                             <&cpu44_intc 3>,
+                                             <&cpu45_intc 3>,
+                                             <&cpu46_intc 3>,
+                                             <&cpu47_intc 3>,
+                                             <&cpu48_intc 3>,
+                                             <&cpu49_intc 3>,
+                                             <&cpu50_intc 3>,
+                                             <&cpu51_intc 3>,
+                                             <&cpu52_intc 3>,
+                                             <&cpu53_intc 3>,
+                                             <&cpu54_intc 3>,
+                                             <&cpu55_intc 3>,
+                                             <&cpu56_intc 3>,
+                                             <&cpu57_intc 3>,
+                                             <&cpu58_intc 3>,
+                                             <&cpu59_intc 3>,
+                                             <&cpu60_intc 3>,
+                                             <&cpu61_intc 3>,
+                                             <&cpu62_intc 3>,
+                                             <&cpu63_intc 3>;
+               };
+
+               clint_mtimer0: timer@70ac000000 {
+                       compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+                       reg = <0x00000070 0xac000000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu0_intc 7>,
+                                             <&cpu1_intc 7>,
+                                             <&cpu2_intc 7>,
+                                             <&cpu3_intc 7>;
+               };
+
+               clint_mtimer1: timer@70ac010000 {
+                       compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+                       reg = <0x00000070 0xac010000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu4_intc 7>,
+                                             <&cpu5_intc 7>,
+                                             <&cpu6_intc 7>,
+                                             <&cpu7_intc 7>;
+               };
+
+               clint_mtimer2: timer@70ac020000 {
+                       compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+                       reg = <0x00000070 0xac020000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu8_intc 7>,
+                                             <&cpu9_intc 7>,
+                                             <&cpu10_intc 7>,
+                                             <&cpu11_intc 7>;
+               };
+
+               clint_mtimer3: timer@70ac030000 {
+                       compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+                       reg = <0x00000070 0xac030000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu12_intc 7>,
+                                             <&cpu13_intc 7>,
+                                             <&cpu14_intc 7>,
+                                             <&cpu15_intc 7>;
+               };
+
+               clint_mtimer4: timer@70ac040000 {
+                       compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+                       reg = <0x00000070 0xac040000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu16_intc 7>,
+                                             <&cpu17_intc 7>,
+                                             <&cpu18_intc 7>,
+                                             <&cpu19_intc 7>;
+               };
+
+               clint_mtimer5: timer@70ac050000 {
+                       compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+                       reg = <0x00000070 0xac050000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu20_intc 7>,
+                                             <&cpu21_intc 7>,
+                                             <&cpu22_intc 7>,
+                                             <&cpu23_intc 7>;
+               };
+
+               clint_mtimer6: timer@70ac060000 {
+                       compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+                       reg = <0x00000070 0xac060000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu24_intc 7>,
+                                             <&cpu25_intc 7>,
+                                             <&cpu26_intc 7>,
+                                             <&cpu27_intc 7>;
+               };
+
+               clint_mtimer7: timer@70ac070000 {
+                       compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+                       reg = <0x00000070 0xac070000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu28_intc 7>,
+                                             <&cpu29_intc 7>,
+                                             <&cpu30_intc 7>,
+                                             <&cpu31_intc 7>;
+               };
+
+               clint_mtimer8: timer@70ac080000 {
+                       compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+                       reg = <0x00000070 0xac080000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu32_intc 7>,
+                                             <&cpu33_intc 7>,
+                                             <&cpu34_intc 7>,
+                                             <&cpu35_intc 7>;
+               };
+
+               clint_mtimer9: timer@70ac090000 {
+                       compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+                       reg = <0x00000070 0xac090000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu36_intc 7>,
+                                             <&cpu37_intc 7>,
+                                             <&cpu38_intc 7>,
+                                             <&cpu39_intc 7>;
+               };
+
+               clint_mtimer10: timer@70ac0a0000 {
+                       compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+                       reg = <0x00000070 0xac0a0000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu40_intc 7>,
+                                             <&cpu41_intc 7>,
+                                             <&cpu42_intc 7>,
+                                             <&cpu43_intc 7>;
+               };
+
+               clint_mtimer11: timer@70ac0b0000 {
+                       compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+                       reg = <0x00000070 0xac0b0000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu44_intc 7>,
+                                             <&cpu45_intc 7>,
+                                             <&cpu46_intc 7>,
+                                             <&cpu47_intc 7>;
+               };
+
+               clint_mtimer12: timer@70ac0c0000 {
+                       compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+                       reg = <0x00000070 0xac0c0000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu48_intc 7>,
+                                             <&cpu49_intc 7>,
+                                             <&cpu50_intc 7>,
+                                             <&cpu51_intc 7>;
+               };
+
+               clint_mtimer13: timer@70ac0d0000 {
+                       compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+                       reg = <0x00000070 0xac0d0000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu52_intc 7>,
+                                             <&cpu53_intc 7>,
+                                             <&cpu54_intc 7>,
+                                             <&cpu55_intc 7>;
+               };
+
+               clint_mtimer14: timer@70ac0e0000 {
+                       compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+                       reg = <0x00000070 0xac0e0000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu56_intc 7>,
+                                             <&cpu57_intc 7>,
+                                             <&cpu58_intc 7>,
+                                             <&cpu59_intc 7>;
+               };
+
+               clint_mtimer15: timer@70ac0f0000 {
+                       compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+                       reg = <0x00000070 0xac0f0000 0x00000000 0x00007ff8>;
+                       interrupts-extended = <&cpu60_intc 7>,
+                                             <&cpu61_intc 7>,
+                                             <&cpu62_intc 7>,
+                                             <&cpu63_intc 7>;
+               };
+
+               intc: interrupt-controller@7090000000 {
+                       compatible = "sophgo,sg2042-plic", "thead,c900-plic";
+                       #address-cells = <0>;
+                       #interrupt-cells = <2>;
+                       reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
+                       interrupt-controller;
+                       interrupts-extended =
+                               <&cpu0_intc 11>,  <&cpu0_intc 9>,
+                               <&cpu1_intc 11>,  <&cpu1_intc 9>,
+                               <&cpu2_intc 11>,  <&cpu2_intc 9>,
+                               <&cpu3_intc 11>,  <&cpu3_intc 9>,
+                               <&cpu4_intc 11>,  <&cpu4_intc 9>,
+                               <&cpu5_intc 11>,  <&cpu5_intc 9>,
+                               <&cpu6_intc 11>,  <&cpu6_intc 9>,
+                               <&cpu7_intc 11>,  <&cpu7_intc 9>,
+                               <&cpu8_intc 11>,  <&cpu8_intc 9>,
+                               <&cpu9_intc 11>,  <&cpu9_intc 9>,
+                               <&cpu10_intc 11>, <&cpu10_intc 9>,
+                               <&cpu11_intc 11>, <&cpu11_intc 9>,
+                               <&cpu12_intc 11>, <&cpu12_intc 9>,
+                               <&cpu13_intc 11>, <&cpu13_intc 9>,
+                               <&cpu14_intc 11>, <&cpu14_intc 9>,
+                               <&cpu15_intc 11>, <&cpu15_intc 9>,
+                               <&cpu16_intc 11>, <&cpu16_intc 9>,
+                               <&cpu17_intc 11>, <&cpu17_intc 9>,
+                               <&cpu18_intc 11>, <&cpu18_intc 9>,
+                               <&cpu19_intc 11>, <&cpu19_intc 9>,
+                               <&cpu20_intc 11>, <&cpu20_intc 9>,
+                               <&cpu21_intc 11>, <&cpu21_intc 9>,
+                               <&cpu22_intc 11>, <&cpu22_intc 9>,
+                               <&cpu23_intc 11>, <&cpu23_intc 9>,
+                               <&cpu24_intc 11>, <&cpu24_intc 9>,
+                               <&cpu25_intc 11>, <&cpu25_intc 9>,
+                               <&cpu26_intc 11>, <&cpu26_intc 9>,
+                               <&cpu27_intc 11>, <&cpu27_intc 9>,
+                               <&cpu28_intc 11>, <&cpu28_intc 9>,
+                               <&cpu29_intc 11>, <&cpu29_intc 9>,
+                               <&cpu30_intc 11>, <&cpu30_intc 9>,
+                               <&cpu31_intc 11>, <&cpu31_intc 9>,
+                               <&cpu32_intc 11>, <&cpu32_intc 9>,
+                               <&cpu33_intc 11>, <&cpu33_intc 9>,
+                               <&cpu34_intc 11>, <&cpu34_intc 9>,
+                               <&cpu35_intc 11>, <&cpu35_intc 9>,
+                               <&cpu36_intc 11>, <&cpu36_intc 9>,
+                               <&cpu37_intc 11>, <&cpu37_intc 9>,
+                               <&cpu38_intc 11>, <&cpu38_intc 9>,
+                               <&cpu39_intc 11>, <&cpu39_intc 9>,
+                               <&cpu40_intc 11>, <&cpu40_intc 9>,
+                               <&cpu41_intc 11>, <&cpu41_intc 9>,
+                               <&cpu42_intc 11>, <&cpu42_intc 9>,
+                               <&cpu43_intc 11>, <&cpu43_intc 9>,
+                               <&cpu44_intc 11>, <&cpu44_intc 9>,
+                               <&cpu45_intc 11>, <&cpu45_intc 9>,
+                               <&cpu46_intc 11>, <&cpu46_intc 9>,
+                               <&cpu47_intc 11>, <&cpu47_intc 9>,
+                               <&cpu48_intc 11>, <&cpu48_intc 9>,
+                               <&cpu49_intc 11>, <&cpu49_intc 9>,
+                               <&cpu50_intc 11>, <&cpu50_intc 9>,
+                               <&cpu51_intc 11>, <&cpu51_intc 9>,
+                               <&cpu52_intc 11>, <&cpu52_intc 9>,
+                               <&cpu53_intc 11>, <&cpu53_intc 9>,
+                               <&cpu54_intc 11>, <&cpu54_intc 9>,
+                               <&cpu55_intc 11>, <&cpu55_intc 9>,
+                               <&cpu56_intc 11>, <&cpu56_intc 9>,
+                               <&cpu57_intc 11>, <&cpu57_intc 9>,
+                               <&cpu58_intc 11>, <&cpu58_intc 9>,
+                               <&cpu59_intc 11>, <&cpu59_intc 9>,
+                               <&cpu60_intc 11>, <&cpu60_intc 9>,
+                               <&cpu61_intc 11>, <&cpu61_intc 9>,
+                               <&cpu62_intc 11>, <&cpu62_intc 9>,
+                               <&cpu63_intc 11>, <&cpu63_intc 9>;
+                       riscv,ndev = <224>;
+               };
+
+               uart0: serial@7040000000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
+                       interrupt-parent = <&intc>;
+                       interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-frequency = <500000000>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       status = "disabled";
+               };
+       };
+};