status = "disabled";
                };
 
-               can3: can@40003400 {
-                       compatible = "st,stm32f4-bxcan";
-                       reg = <0x40003400 0x200>;
-                       interrupts = <104>, <105>, <106>, <107>;
-                       interrupt-names = "tx", "rx0", "rx1", "sce";
-                       resets = <&rcc STM32F7_APB1_RESET(CAN3)>;
-                       clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
-                       st,gcan = <&gcan3>;
-                       status = "disabled";
-               };
-
-               gcan3: gcan@40003600 {
-                       compatible = "st,stm32f4-gcan", "syscon";
-                       reg = <0x40003600 0x200>;
-                       clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
-               };
-
                spi2: spi@40003800 {
                        #address-cells = <1>;
                        #size-cells = <0>;
 
 
 / {
        soc {
+               can3: can@40003400 {
+                       compatible = "st,stm32f4-bxcan";
+                       reg = <0x40003400 0x200>;
+                       interrupts = <104>, <105>, <106>, <107>;
+                       interrupt-names = "tx", "rx0", "rx1", "sce";
+                       resets = <&rcc STM32F7_APB1_RESET(CAN3)>;
+                       clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
+                       st,gcan = <&gcan3>;
+                       status = "disabled";
+               };
+
+               gcan3: gcan@40003600 {
+                       compatible = "st,stm32f4-gcan", "syscon";
+                       reg = <0x40003600 0x200>;
+                       clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
+               };
+
                dsi: dsi@40016c00 {
                        compatible = "st,stm32-dsi";
                        reg = <0x40016c00 0x800>;