drm/i915: Bump DSL linemask to 20 bits

Since tgl PIPE_DSL has 20 bits for the scanline. Let's bump our
definition to match. And while at it let's also add the define
for the current field readback.

We can also get rid of the gen2 vs. gen3+ nonsense since none
of the extra bits ever did anything and just always read
as zero. And now we extend all platforms to use the tgl+
20 bits deinition, but again that is fine since all the bits
used to be mbz and always read as zero on all the platforms.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211112193813.8224-2-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 69244ad19eec045eee66129b2fae36b845d2d463..311390af1300d584b7896124b8866b7d6359fcbd 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -353,16 +353,10 @@ static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
 {
        i915_reg_t reg = PIPEDSL(pipe);
        u32 line1, line2;
-       u32 line_mask;
 
-       if (DISPLAY_VER(dev_priv) == 2)
-               line_mask = DSL_LINEMASK_GEN2;
-       else
-               line_mask = DSL_LINEMASK_GEN3;
-
-       line1 = intel_de_read(dev_priv, reg) & line_mask;
+       line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
        msleep(5);
-       line2 = intel_de_read(dev_priv, reg) & line_mask;
+       line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
 
        return line1 != line2;
 }

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 71171338f2dfdb6b1e9afb4ea56b41bdd1b11516..14ae4f9b3fa698b9f641171396228c99155ca2ae 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -836,10 +836,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
        if (mode->flags & DRM_MODE_FLAG_INTERLACE)
                vtotal /= 2;
 
-       if (DISPLAY_VER(dev_priv) == 2)
-               position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
-       else
-               position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
+       position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK;
 
        /*
         * On HSW, the DSL reg (0x70000) appears to return 0 if we
@@ -858,7 +855,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 
                for (i = 0; i < 100; i++) {
                        udelay(1);
-                       temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
+                       temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK;
                        if (temp != position) {
                                position = temp;
                                break;

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cf168c3e0471e81ebc91f5f0e8f8460b14ee8894..507cc3d54fe8340f6fe3bb457cc12b31bf7df2ab 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5165,8 +5165,8 @@ enum {
 
 /* Pipe A */
 #define _PIPEADSL              0x70000
-#define   DSL_LINEMASK_GEN2    0x00000fff
-#define   DSL_LINEMASK_GEN3    0x00001fff
+#define   PIPEDSL_CURR_FIELD   REG_BIT(31) /* ctg+ */
+#define   PIPEDSL_LINE_MASK    REG_GENMASK(19, 0)
 #define _PIPEACONF             0x70008
 #define   PIPECONF_ENABLE      (1 << 31)
 #define   PIPECONF_DISABLE     0