drm/msm/dpu: Enable widebus for DSI INTF

DPU supports a data-bus widen mode for DSI INTF.

Enable this mode for all supported chipsets if widebus is enabled for DSI.

Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/553756/
Link: https://lore.kernel.org/r/20230822-add-widebus-support-v4-2-9dc86083d6ea@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 3c0b31adb7165ca9514dc0e31316c0a23bf8e745..1cf7ff6caff4efd80bcc6a6394b9adb4851078ed 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1196,15 +1196,18 @@ static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc,
        struct drm_display_mode *cur_mode = NULL;
        struct msm_drm_private *priv = drm_enc->dev->dev_private;
        struct msm_display_info *disp_info;
+       int index;
 
        dpu_enc = to_dpu_encoder_virt(drm_enc);
        disp_info = &dpu_enc->disp_info;
+       index = disp_info->h_tile_instance[0];
 
        dpu_enc->dsc = dpu_encoder_get_dsc_config(drm_enc);
 
        if (disp_info->intf_type == INTF_DP)
-               dpu_enc->wide_bus_en = msm_dp_wide_bus_available(
-                               priv->dp[disp_info->h_tile_instance[0]]);
+               dpu_enc->wide_bus_en = msm_dp_wide_bus_available(priv->dp[index]);
+       else if (disp_info->intf_type == INTF_DSI)
+               dpu_enc->wide_bus_en = msm_dsi_wide_bus_enabled(priv->dsi[index]);
 
        mutex_lock(&dpu_enc->enc_lock);
        cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 9589fe71945211cb924500e36d14f8fe76066455..cab7a32d1c29b815af17ec9ca3767d1aff23156d 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -72,6 +72,8 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
        if (intf_cfg.dsc != 0)
                cmd_mode_cfg.data_compress = true;
 
+       cmd_mode_cfg.wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent);
+
        if (phys_enc->hw_intf->ops.program_intf_cmd_cfg)
                phys_enc->hw_intf->ops.program_intf_cmd_cfg(phys_enc->hw_intf, &cmd_mode_cfg);
 }

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 8ec6505d9e7860975e65c4476954e403617c8fd6..5dcc83dd47ef1058dbc51e36423a609c34848676 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -521,6 +521,9 @@ static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *ctx,
        if (cmd_mode_cfg->data_compress)
                intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
 
+       if (cmd_mode_cfg->wide_bus_en)
+               intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN;
+
        DPU_REG_WRITE(&ctx->hw, INTF_CONFIG2, intf_cfg2);
 }
 
@@ -545,6 +548,10 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
                ops->disable_autorefresh = dpu_hw_intf_disable_autorefresh;
        }
 
+       /* Technically, INTF_CONFIG2 is present for DPU 5.0+, but
+        * we can configure it for DPU 7.0+ since the wide bus and DSC flags
+        * would not be set for DPU < 7.0 anyways
+        */
        if (mdss_rev->core_major_ver >= 7)
                ops->program_intf_cmd_cfg = dpu_hw_intf_program_intf_cmd_cfg;
 }

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
index 77f80531782b5965d3e6018b86cbd78407ccb0f2..c539025c418bb1d2dd775ffd2b24f3536e1a14ca 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
@@ -50,6 +50,7 @@ struct dpu_hw_intf_status {
 
 struct dpu_hw_intf_cmd_mode_cfg {
        u8 data_compress;       /* enable data compress between dpu and dsi */
+       u8 wide_bus_en;         /* enable databus widen mode */
 };
 
 /**

diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
index baab79ab6e745efee6690a9cc7d6c5df5f9a6321..4cf424b3509f4a6a0b01b8af46b66b59540a1738 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/dsi.c
+++ b/drivers/gpu/drm/msm/dsi/dsi.c
@@ -17,6 +17,11 @@ struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
        return msm_dsi_host_get_dsc_config(msm_dsi->host);
 }
 
+bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi)
+{
+       return false;
+}
+
 static int dsi_get_phy(struct msm_dsi *msm_dsi)
 {
        struct platform_device *pdev = msm_dsi->pdev;

diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 02fd6c7d0bb7b944628a10e82f12039db2c7c556..5eda9f04de0de9ee07f55d3da35bbf702f97741a 100644 (file)
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -343,6 +343,7 @@ void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi
 bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi);
 bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi);
 bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi);
+bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi);
 struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi);
 #else
 static inline void __init msm_dsi_register(void)
@@ -372,6 +373,10 @@ static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi)
 {
        return false;
 }
+static inline bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi)
+{
+       return false;
+}
 
 static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
 {