ARM: dts: qcom: sdx65: Enable ARM SMMU

Add a node for the ARM SMMU found in the SDX65.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1649670615-21268-6-git-send-email-quic_rohiagar@quicinc.com

diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 77bca58d88c1c81a9d84df332618c709928310e2..f50a8a404ce0f6b009626f50bce0244c66eb8528 100644 (file)
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -190,6 +190,46 @@
                        interrupt-controller;
                };
 
+               apps_smmu: iommu@15000000 {
+                       compatible = "qcom,sdx65-smmu-500", "arm,mmu-500";
+                       reg = <0x15000000 0x40000>;
+                       #iommu-cells = <2>;
+                       #global-interrupts = <1>;
+                       interrupts =    <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
                intc: interrupt-controller@17800000 {
                        compatible = "qcom,msm-qgic2";
                        interrupt-controller;