arm64: dts: rockchip: add pwm nodes for rk3568

Add the pwm controller nodes to the core rk3568 dtsi.

Signed-off-by: Liang Chen <cl@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20210726090355.1548483-2-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index ec73e8783d425480a0a5e18e732a0128dba61c16..b721a34ffa8cd0a1d2d5c0eff6736a51fec9b945 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -263,6 +263,50 @@
                status = "disabled";
        };
 
+       pwm0: pwm@fdd70000 {
+               compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+               reg = <0x0 0xfdd70000 0x0 0x10>;
+               clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
+               clock-names = "pwm", "pclk";
+               pinctrl-0 = <&pwm0m0_pins>;
+               pinctrl-names = "active";
+               #pwm-cells = <3>;
+               status = "disabled";
+       };
+
+       pwm1: pwm@fdd70010 {
+               compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+               reg = <0x0 0xfdd70010 0x0 0x10>;
+               clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
+               clock-names = "pwm", "pclk";
+               pinctrl-0 = <&pwm1m0_pins>;
+               pinctrl-names = "active";
+               #pwm-cells = <3>;
+               status = "disabled";
+       };
+
+       pwm2: pwm@fdd70020 {
+               compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+               reg = <0x0 0xfdd70020 0x0 0x10>;
+               clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
+               clock-names = "pwm", "pclk";
+               pinctrl-0 = <&pwm2m0_pins>;
+               pinctrl-names = "active";
+               #pwm-cells = <3>;
+               status = "disabled";
+       };
+
+       pwm3: pwm@fdd70030 {
+               compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+               reg = <0x0 0xfdd70030 0x0 0x10>;
+               clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
+               clock-names = "pwm", "pclk";
+               pinctrl-0 = <&pwm3_pins>;
+               pinctrl-names = "active";
+               #pwm-cells = <3>;
+               status = "disabled";
+       };
+
        pmu: power-management@fdd90000 {
                compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
                reg = <0x0 0xfdd90000 0x0 0x1000>;
@@ -863,6 +907,138 @@
                status = "disabled";
        };
 
+       pwm4: pwm@fe6e0000 {
+               compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+               reg = <0x0 0xfe6e0000 0x0 0x10>;
+               clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+               clock-names = "pwm", "pclk";
+               pinctrl-0 = <&pwm4_pins>;
+               pinctrl-names = "active";
+               #pwm-cells = <3>;
+               status = "disabled";
+       };
+
+       pwm5: pwm@fe6e0010 {
+               compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+               reg = <0x0 0xfe6e0010 0x0 0x10>;
+               clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+               clock-names = "pwm", "pclk";
+               pinctrl-0 = <&pwm5_pins>;
+               pinctrl-names = "active";
+               #pwm-cells = <3>;
+               status = "disabled";
+       };
+
+       pwm6: pwm@fe6e0020 {
+               compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+               reg = <0x0 0xfe6e0020 0x0 0x10>;
+               clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+               clock-names = "pwm", "pclk";
+               pinctrl-0 = <&pwm6_pins>;
+               pinctrl-names = "active";
+               #pwm-cells = <3>;
+               status = "disabled";
+       };
+
+       pwm7: pwm@fe6e0030 {
+               compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+               reg = <0x0 0xfe6e0030 0x0 0x10>;
+               clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+               clock-names = "pwm", "pclk";
+               pinctrl-0 = <&pwm7_pins>;
+               pinctrl-names = "active";
+               #pwm-cells = <3>;
+               status = "disabled";
+       };
+
+       pwm8: pwm@fe6f0000 {
+               compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+               reg = <0x0 0xfe6f0000 0x0 0x10>;
+               clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
+               clock-names = "pwm", "pclk";
+               pinctrl-0 = <&pwm8m0_pins>;
+               pinctrl-names = "active";
+               #pwm-cells = <3>;
+               status = "disabled";
+       };
+
+       pwm9: pwm@fe6f0010 {
+               compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+               reg = <0x0 0xfe6f0010 0x0 0x10>;
+               clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
+               clock-names = "pwm", "pclk";
+               pinctrl-0 = <&pwm9m0_pins>;
+               pinctrl-names = "active";
+               #pwm-cells = <3>;
+               status = "disabled";
+       };
+
+       pwm10: pwm@fe6f0020 {
+               compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+               reg = <0x0 0xfe6f0020 0x0 0x10>;
+               clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
+               clock-names = "pwm", "pclk";
+               pinctrl-0 = <&pwm10m0_pins>;
+               pinctrl-names = "active";
+               #pwm-cells = <3>;
+               status = "disabled";
+       };
+
+       pwm11: pwm@fe6f0030 {
+               compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+               reg = <0x0 0xfe6f0030 0x0 0x10>;
+               clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
+               clock-names = "pwm", "pclk";
+               pinctrl-0 = <&pwm11m0_pins>;
+               pinctrl-names = "active";
+               #pwm-cells = <3>;
+               status = "disabled";
+       };
+
+       pwm12: pwm@fe700000 {
+               compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+               reg = <0x0 0xfe700000 0x0 0x10>;
+               clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
+               clock-names = "pwm", "pclk";
+               pinctrl-0 = <&pwm12m0_pins>;
+               pinctrl-names = "active";
+               #pwm-cells = <3>;
+               status = "disabled";
+       };
+
+       pwm13: pwm@fe700010 {
+               compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+               reg = <0x0 0xfe700010 0x0 0x10>;
+               clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
+               clock-names = "pwm", "pclk";
+               pinctrl-0 = <&pwm13m0_pins>;
+               pinctrl-names = "active";
+               #pwm-cells = <3>;
+               status = "disabled";
+       };
+
+       pwm14: pwm@fe700020 {
+               compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+               reg = <0x0 0xfe700020 0x0 0x10>;
+               clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
+               clock-names = "pwm", "pclk";
+               pinctrl-0 = <&pwm14m0_pins>;
+               pinctrl-names = "active";
+               #pwm-cells = <3>;
+               status = "disabled";
+       };
+
+       pwm15: pwm@fe700030 {
+               compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+               reg = <0x0 0xfe700030 0x0 0x10>;
+               clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
+               clock-names = "pwm", "pclk";
+               pinctrl-0 = <&pwm15m0_pins>;
+               pinctrl-names = "active";
+               #pwm-cells = <3>;
+               status = "disabled";
+       };
+
        pinctrl: pinctrl {
                compatible = "rockchip,rk3568-pinctrl";
                rockchip,grf = <&grf>;