drm/msm/dpu1: Rename sm8150_dspp_blk to sdm845_dspp_blk
authorKonrad Dybcio <konrad.dybcio@linaro.org>
Thu, 20 Apr 2023 01:14:54 +0000 (03:14 +0200)
committerDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Mon, 10 Jul 2023 23:35:42 +0000 (02:35 +0300)
SDM845 was the first SoC to include both PCC v4 and GC v1.8.
We don't currently support any other blocks but the common config
for these two can be reused for a large amount of SoCs.

Rename it to indicate the origin of that combo.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/533003/
Link: https://lore.kernel.org/r/20230420-topic-dpu_gc-v1-1-d9d1a5e40917@linaro.org
[DB: also applied to new catalog files]
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
15 files changed:
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

index b6098141bb9bbfa2266305b6fe704724347431a2..18e27f7550e66fda3391519e0b13ea13ff24dd38 100644 (file)
@@ -111,13 +111,13 @@ static const struct dpu_lm_cfg sdm845_lm[] = {
 
 static const struct dpu_dspp_cfg sdm845_dspp[] = {
        DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
        DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
        DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
        DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
 };
 
 static const struct dpu_pingpong_cfg sdm845_pp[] = {
index b5f75135426781fc13e7839707b8f3ae00bf8a57..a654ba8226cd2432fdec1b4240f3213d5566049c 100644 (file)
@@ -118,13 +118,13 @@ static const struct dpu_lm_cfg sm8150_lm[] = {
 
 static const struct dpu_dspp_cfg sm8150_dspp[] = {
        DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
        DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
        DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
        DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
 };
 
 static const struct dpu_pingpong_cfg sm8150_pp[] = {
index 8ed2b263c5ea3d01cdc4deb472f33612fab483f4..6dd24bd39a68a90b3b44d3ab51f3e5c5e334b57f 100644 (file)
@@ -117,13 +117,13 @@ static const struct dpu_lm_cfg sc8180x_lm[] = {
 
 static const struct dpu_dspp_cfg sc8180x_dspp[] = {
        DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
        DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
        DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
        DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
 };
 
 static const struct dpu_pingpong_cfg sc8180x_pp[] = {
index daebd217004135ba6f3cda0b4b2f07d4593fb526..6a6d37c1dededd1f7a690d67cef80a627a3073d9 100644 (file)
@@ -119,13 +119,13 @@ static const struct dpu_lm_cfg sm8250_lm[] = {
 
 static const struct dpu_dspp_cfg sm8250_dspp[] = {
        DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
        DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
        DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
        DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
 };
 
 static const struct dpu_pingpong_cfg sm8250_pp[] = {
index 67566b07195a2457f94d607e64d8fd14f3706d15..a3124661cb65fd2df28110bbdded327406cbdfe5 100644 (file)
@@ -76,7 +76,7 @@ static const struct dpu_lm_cfg sc7180_lm[] = {
 
 static const struct dpu_dspp_cfg sc7180_dspp[] = {
        DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
 };
 
 static const struct dpu_pingpong_cfg sc7180_pp[] = {
index 031fc8dae3c69852b7a9f26831dabec1a6994caa..04a0dbf96e17982f93d239c2c7eca2fd007c228b 100644 (file)
@@ -56,7 +56,7 @@ static const struct dpu_lm_cfg sm6115_lm[] = {
 
 static const struct dpu_dspp_cfg sm6115_dspp[] = {
        DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
 };
 
 static const struct dpu_pingpong_cfg sm6115_pp[] = {
index 06eba23b02364b6a46394f972ea13d99c6c2aaab..3262a5232b5a35015d6b346c6637914db71ae09b 100644 (file)
@@ -85,7 +85,7 @@ static const struct dpu_lm_cfg sm6350_lm[] = {
 
 static const struct dpu_dspp_cfg sm6350_dspp[] = {
        DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
-               &sm8150_dspp_sblk),
+               &sdm845_dspp_sblk),
 };
 
 static struct dpu_pingpong_cfg sm6350_pp[] = {
index f2808098af39936aab90931e427060c3765b2c68..06cf48b55f989ce4cfd40a40ada40cb094ae8eb5 100644 (file)
@@ -53,7 +53,7 @@ static const struct dpu_lm_cfg qcm2290_lm[] = {
 
 static const struct dpu_dspp_cfg qcm2290_dspp[] = {
        DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
 };
 
 static const struct dpu_pingpong_cfg qcm2290_pp[] = {
index 241fa6746674d914c7f01a905c4b09bc3c6daedd..a01c7ea43c3399f2516678292b4e923bb93b6a8b 100644 (file)
@@ -57,7 +57,7 @@ static const struct dpu_lm_cfg sm6375_lm[] = {
 
 static const struct dpu_dspp_cfg sm6375_dspp[] = {
        DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
-               &sm8150_dspp_sblk),
+               &sdm845_dspp_sblk),
 };
 
 static const struct dpu_pingpong_cfg sm6375_pp[] = {
index 8da424eaee6a2db53802b303e131ef7348ab0021..8f3bf7964ba0413b2c158943970d3b075180def4 100644 (file)
@@ -117,13 +117,13 @@ static const struct dpu_lm_cfg sm8350_lm[] = {
 
 static const struct dpu_dspp_cfg sm8350_dspp[] = {
        DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
        DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
        DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
        DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
 };
 
 static const struct dpu_pingpong_cfg sm8350_pp[] = {
index 900fee410e113adf4fb4a6eb9c25eb512ec879fc..1624e5035a2c35fd874ba6e67a62b1e5f56f7393 100644 (file)
@@ -84,7 +84,7 @@ static const struct dpu_lm_cfg sc7280_lm[] = {
 
 static const struct dpu_dspp_cfg sc7280_dspp[] = {
        DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
 };
 
 static const struct dpu_pingpong_cfg sc7280_pp[] = {
index f6ce6b090f7188632c638ee9d177fe65dd0aad34..1362552027fbc61226dfccd5e6cd2f78becf1168 100644 (file)
@@ -112,13 +112,13 @@ static const struct dpu_lm_cfg sc8280xp_lm[] = {
 
 static const struct dpu_dspp_cfg sc8280xp_dspp[] = {
        DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
        DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
        DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
        DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
 };
 
 static const struct dpu_pingpong_cfg sc8280xp_pp[] = {
index 8d13c369213c071638ecda18c0b623cfbdffae03..c368a216933a4988765933bfaea8944ff8cd5adc 100644 (file)
@@ -118,13 +118,13 @@ static const struct dpu_lm_cfg sm8450_lm[] = {
 
 static const struct dpu_dspp_cfg sm8450_dspp[] = {
        DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
        DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
        DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
        DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
 };
 
 static const struct dpu_pingpong_cfg sm8450_pp[] = {
index f17b9a7fee851ff2a40ab616913d9f3b145f0352..22096c1a828779d5bae711a36cbddc5480d27086 100644 (file)
@@ -123,13 +123,13 @@ static const struct dpu_lm_cfg sm8550_lm[] = {
 
 static const struct dpu_dspp_cfg sm8550_dspp[] = {
        DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
        DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
        DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
        DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
-                &sm8150_dspp_sblk),
+                &sdm845_dspp_sblk),
 };
 static const struct dpu_pingpong_cfg sm8550_pp[] = {
        PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk,
index 0de507d4d7b7a26870044501b2af0efce630bdfb..8d5f83321be21b24db49688327443924d78d40d1 100644 (file)
@@ -448,7 +448,7 @@ static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = {
                .len = 0x90, .version = 0x10007},
 };
 
-static const struct dpu_dspp_sub_blks sm8150_dspp_sblk = {
+static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = {
        .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700,
                .len = 0x90, .version = 0x40000},
 };