drm/etnaviv: add SH perf domain

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

diff --git a/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c b/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
index 9f933feabff23b24abede2859313aa1e77d88e51..cdc02c3be64ee50afd6549cd67ffadd959421e71 100644 (file)
--- a/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
@@ -147,6 +147,59 @@ static const struct etnaviv_pm_domain doms_3d[] = {
                                &pipe_reg_read
                        }
                }
+       },
+       {
+               .name = "SH",
+               .profile_read = VIVS_MC_PROFILE_SH_READ,
+               .profile_config = VIVS_MC_PROFILE_CONFIG0,
+               .nr_signals = 9,
+               .signal = (const struct etnaviv_pm_signal[]) {
+                       {
+                               "SHADER_CYCLES",
+                               VIVS_MC_PROFILE_CONFIG0_SH_SHADER_CYCLES,
+                               &perf_reg_read
+                       },
+                       {
+                               "PS_INST_COUNTER",
+                               VIVS_MC_PROFILE_CONFIG0_SH_PS_INST_COUNTER,
+                               &perf_reg_read
+                       },
+                       {
+                               "RENDERED_PIXEL_COUNTER",
+                               VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_PIXEL_COUNTER,
+                               &perf_reg_read
+                       },
+                       {
+                               "VS_INST_COUNTER",
+                               VIVS_MC_PROFILE_CONFIG0_SH_VS_INST_COUNTER,
+                               &pipe_reg_read
+                       },
+                       {
+                               "RENDERED_VERTICE_COUNTER",
+                               VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_VERTICE_COUNTER,
+                               &pipe_reg_read
+                       },
+                       {
+                               "VTX_BRANCH_INST_COUNTER",
+                               VIVS_MC_PROFILE_CONFIG0_SH_VTX_BRANCH_INST_COUNTER,
+                               &pipe_reg_read
+                       },
+                       {
+                               "VTX_TEXLD_INST_COUNTER",
+                               VIVS_MC_PROFILE_CONFIG0_SH_VTX_TEXLD_INST_COUNTER,
+                               &pipe_reg_read
+                       },
+                       {
+                               "PXL_BRANCH_INST_COUNTER",
+                               VIVS_MC_PROFILE_CONFIG0_SH_PXL_BRANCH_INST_COUNTER,
+                               &pipe_reg_read
+                       },
+                       {
+                               "PXL_TEXLD_INST_COUNTER",
+                               VIVS_MC_PROFILE_CONFIG0_SH_PXL_TEXLD_INST_COUNTER,
+                               &pipe_reg_read
+                       }
+               }
        }
 };