RISC-V: KVM: No need to update the counter value during reset

The virtual counter value is updated during pmu_ctr_read. There is no need
to update it in reset case. Otherwise, it will be counted twice which is
incorrect.

Fixes: 0cb74b65d2e5 ("RISC-V: KVM: Implement perf support without sampling")
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20240420151741.962500-12-atishp@rivosinc.com
Signed-off-by: Anup Patel <anup@brainfault.org>

diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c
index cee1b9ca4ec481c4abd67912b0731b42f70456e1..b5159ce4592dc3715457f96efb76bbd529272876 100644 (file)
--- a/arch/riscv/kvm/vcpu_pmu.c
+++ b/arch/riscv/kvm/vcpu_pmu.c
@@ -397,7 +397,6 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_base,
 {
        struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
        int i, pmc_index, sbiret = 0;
-       u64 enabled, running;
        struct kvm_pmc *pmc;
        int fevent_code;
 
@@ -432,12 +431,9 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_base,
                                sbiret = SBI_ERR_ALREADY_STOPPED;
                        }
 
-                       if (flags & SBI_PMU_STOP_FLAG_RESET) {
-                               /* Relase the counter if this is a reset request */
-                               pmc->counter_val += perf_event_read_value(pmc->perf_event,
-                                                                         &enabled, &running);
+                       if (flags & SBI_PMU_STOP_FLAG_RESET)
+                               /* Release the counter if this is a reset request */
                                kvm_pmu_release_perf_event(pmc);
-                       }
                } else {
                        sbiret = SBI_ERR_INVALID_PARAM;
                }