drm/amd/display: change fastboot timing validation

[Why]
VBIOS light up eDP with 6bpc but driver use 8bpc without
disable valid stream then re-enable valid stream. Some
panels can't runtime change color depth.

[How]
Change fastboot timing validation function. Not only check
LANE_COUNT, LINK_RATE...etc

Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Paul Hsieh <paul.hsieh@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f616d11250a284bc4f7c1b2661e4f2bd946f877f..83fc03a5c9cd6e204da972c4a1be321d9e58a159 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1462,7 +1462,7 @@ static bool context_changed(
        return false;
 }
 
-bool dc_validate_seamless_boot_timing(const struct dc *dc,
+bool dc_validate_boot_timing(const struct dc *dc,
                                const struct dc_sink *sink,
                                struct dc_crtc_timing *crtc_timing)
 {

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 9df66501a453b250519fe00230381cc0e567da04..b36bae4b5bc99fd03f321fab4fafe28260ca5a0d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2168,7 +2168,7 @@ static void mark_seamless_boot_stream(
 
        if (dc->config.allow_seamless_boot_optimization &&
                        !dcb->funcs->is_accelerated_mode(dcb)) {
-               if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing))
+               if (dc_validate_boot_timing(dc, stream->sink, &stream->timing))
                        stream->apply_seamless_boot_optimization = true;
        }
 }

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index af0587790776888dbdc1b6070557737ad9b6ebf8..cba150ceacbf5d547ea41ef77e7edcda7f3a367a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1126,7 +1126,7 @@ struct dc_validation_set {
        uint8_t plane_count;
 };
 
-bool dc_validate_seamless_boot_timing(const struct dc *dc,
+bool dc_validate_boot_timing(const struct dc *dc,
                                const struct dc_sink *sink,
                                struct dc_crtc_timing *crtc_timing);
 

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 8c32b9cb3b4920d7d5164dfb17c85953f07ccbef..52b22a944f948d87d94bca51c4c608407cb86af1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1761,7 +1761,8 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
                            edp_link->link_status.link_active) {
                                struct dc_stream_state *edp_stream = edp_streams[0];
 
-                               can_apply_edp_fast_boot = !is_edp_ilr_optimization_required(edp_stream->link, &edp_stream->timing);
+                               can_apply_edp_fast_boot = dc_validate_boot_timing(dc,
+                                       edp_stream->sink, &edp_stream->timing);
                                edp_stream->apply_edp_fast_boot_optimization = can_apply_edp_fast_boot;
                                if (can_apply_edp_fast_boot)
                                        DC_LOG_EVENT_LINK_TRAINING("eDP fast boot disabled to optimize link rate\n");