arm64: dts: qcom: sm8650: Add DisplayPort device nodes

Declare the displayport controller present on the Qualcomm SM8650 SoC
and connected to the USB3/DP Combo PHY.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231208-topic-sm8650-upstream-dp-v2-1-69dab3d074e4@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index af5e0a75b0abb0c848c42c15a10d13bdd4471aa2..425e1e50d9455d7701bcd7d1194081d95a673ffa 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -3146,6 +3146,14 @@
                                                        remote-endpoint = <&mdss_dsi1_in>;
                                                };
                                        };
+
+                                       port@2 {
+                                               reg = <2>;
+
+                                               dpu_intf0_out: endpoint {
+                                                       remote-endpoint = <&mdss_dp0_in>;
+                                               };
+                                       };
                                };
 
                                mdp_opp_table: opp-table {
@@ -3347,6 +3355,88 @@
 
                                status = "disabled";
                        };
+
+                       mdss_dp0: displayport-controller@af54000 {
+                               compatible = "qcom,sm8650-dp";
+                               reg = <0 0xaf54000 0 0x104>,
+                                     <0 0xaf54200 0 0xc0>,
+                                     <0 0xaf55000 0 0x770>,
+                                     <0 0xaf56000 0 0x9c>,
+                                     <0 0xaf57000 0 0x9c>;
+
+                               interrupts-extended = <&mdss 12>;
+
+                               clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                                        <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
+                                        <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
+                                        <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
+                                        <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+                               clock-names = "core_iface",
+                                             "core_aux",
+                                             "ctrl_link",
+                                             "ctrl_link_iface",
+                                             "stream_pixel";
+
+                               assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+                                                 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+                               assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+                                                        <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+
+                               operating-points-v2 = <&dp_opp_table>;
+
+                               power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+                               phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
+                               phy-names = "dp";
+
+                               #sound-dai-cells = <0>;
+
+                               status = "disabled";
+
+                               dp_opp_table: opp-table {
+                                       compatible = "operating-points-v2";
+
+                                       opp-162000000 {
+                                               opp-hz = /bits/ 64 <162000000>;
+                                               required-opps = <&rpmhpd_opp_low_svs_d1>;
+                                       };
+
+                                       opp-270000000 {
+                                               opp-hz = /bits/ 64 <270000000>;
+                                               required-opps = <&rpmhpd_opp_low_svs>;
+                                       };
+
+                                       opp-540000000 {
+                                               opp-hz = /bits/ 64 <540000000>;
+                                               required-opps = <&rpmhpd_opp_svs_l1>;
+                                       };
+
+                                       opp-810000000 {
+                                               opp-hz = /bits/ 64 <810000000>;
+                                               required-opps = <&rpmhpd_opp_nom>;
+                                       };
+                               };
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+
+                                               mdss_dp0_in: endpoint {
+                                                       remote-endpoint = <&dpu_intf0_out>;
+                                               };
+                                       };
+
+                                       port@1 {
+                                               reg = <1>;
+
+                                               mdss_dp0_out: endpoint {
+                                               };
+                                       };
+                               };
+                       };
                };
 
                dispcc: clock-controller@af00000 {
@@ -3361,8 +3451,8 @@
                                 <&mdss_dsi0_phy 1>,
                                 <&mdss_dsi1_phy 0>,
                                 <&mdss_dsi1_phy 1>,
-                                <0>, /* dp0 */
-                                <0>,
+                                <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+                                <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
                                 <0>, /* dp1 */
                                 <0>,
                                 <0>, /* dp2 */
@@ -3419,6 +3509,32 @@
                        #phy-cells = <1>;
 
                        status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+
+                                       usb_dp_qmpphy_out: endpoint {
+                                       };
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+
+                                       usb_dp_qmpphy_usb_ss_in: endpoint {
+                                       };
+                               };
+
+                               port@2 {
+                                       reg = <2>;
+
+                                       usb_dp_qmpphy_dp_in: endpoint {
+                                       };
+                               };
+                       };
                };
 
                usb_1: usb@a6f8800 {