pinctrl: mediatek: Fix the drive register definition of some Pins

[ Upstream commit 5754a1c98b18009cb3030dc391aa37b77428a0bd ]

The drive adjustment register definition of gpio13 and gpio81 is wrong:
"the start address for the range" of gpio18 is corrected to 0x000,
"the start bit for the first register within the range" of gpio81 is
corrected to 24.

Fixes: 6cf5e9ef362a ("pinctrl: add pinctrl driver on mt8195")
Signed-off-by: Guodong Liu <Guodong.Liu@mediatek.com>
Link: https://lore.kernel.org/r/20230118062116.26315-1-Guodong.Liu@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8195.c b/drivers/pinctrl/mediatek/pinctrl-mt8195.c
index a7500e18bb1de47129d577a029c88e13636259a4..c32884fc7de799eb0248d69a05c0e2187ef48c33 100644 (file)
--- a/drivers/pinctrl/mediatek/pinctrl-mt8195.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8195.c
@@ -659,7 +659,7 @@ static const struct mtk_pin_field_calc mt8195_pin_drv_range[] = {
        PIN_FIELD_BASE(10, 10, 4, 0x010, 0x10, 9, 3),
        PIN_FIELD_BASE(11, 11, 4, 0x000, 0x10, 24, 3),
        PIN_FIELD_BASE(12, 12, 4, 0x010, 0x10, 12, 3),
-       PIN_FIELD_BASE(13, 13, 4, 0x010, 0x10, 27, 3),
+       PIN_FIELD_BASE(13, 13, 4, 0x000, 0x10, 27, 3),
        PIN_FIELD_BASE(14, 14, 4, 0x010, 0x10, 15, 3),
        PIN_FIELD_BASE(15, 15, 4, 0x010, 0x10, 0, 3),
        PIN_FIELD_BASE(16, 16, 4, 0x010, 0x10, 18, 3),
@@ -708,7 +708,7 @@ static const struct mtk_pin_field_calc mt8195_pin_drv_range[] = {
        PIN_FIELD_BASE(78, 78, 3, 0x000, 0x10, 15, 3),
        PIN_FIELD_BASE(79, 79, 3, 0x000, 0x10, 18, 3),
        PIN_FIELD_BASE(80, 80, 3, 0x000, 0x10, 21, 3),
-       PIN_FIELD_BASE(81, 81, 3, 0x000, 0x10, 28, 3),
+       PIN_FIELD_BASE(81, 81, 3, 0x000, 0x10, 24, 3),
        PIN_FIELD_BASE(82, 82, 3, 0x000, 0x10, 27, 3),
        PIN_FIELD_BASE(83, 83, 3, 0x010, 0x10, 0, 3),
        PIN_FIELD_BASE(84, 84, 3, 0x010, 0x10, 3, 3),