KVM: arm64: nv: Correctly handle negative polarity FGTs

Negative trap bits are a massive pain. They are, on the surface,
indistinguishable from RES0 bits. Do you trap? or do you ignore?

Thankfully, we now have the right infrastructure to check for RES0
bits as long as the register is backed by VNCR, which is the case
for the FGT registers.

Use that information as a discriminant when handling a trap that
is potentially caused by a FGT.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20240214131827.2856277-10-maz@kernel.org
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>

diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
index 8a1cfcf553a29022e6364b3d888bc272d04fb565..ef46c2e4530700262b62f43a1c5809a2c6e95b79 100644 (file)
--- a/arch/arm64/kvm/emulate-nested.c
+++ b/arch/arm64/kvm/emulate-nested.c
@@ -1892,9 +1892,61 @@ static enum trap_behaviour compute_trap_behaviour(struct kvm_vcpu *vcpu,
        return __compute_trap_behaviour(vcpu, tc.cgt, b);
 }
 
-static bool check_fgt_bit(u64 val, const union trap_config tc)
+static u64 kvm_get_sysreg_res0(struct kvm *kvm, enum vcpu_sysreg sr)
 {
-       return ((val >> tc.bit) & 1) == tc.pol;
+       struct kvm_sysreg_masks *masks;
+
+       /* Only handle the VNCR-backed regs for now */
+       if (sr < __VNCR_START__)
+               return 0;
+
+       masks = kvm->arch.sysreg_masks;
+
+       return masks->mask[sr - __VNCR_START__].res0;
+}
+
+static bool check_fgt_bit(struct kvm *kvm, bool is_read,
+                         u64 val, const union trap_config tc)
+{
+       enum vcpu_sysreg sr;
+
+       if (tc.pol)
+               return (val & BIT(tc.bit));
+
+       /*
+        * FGTs with negative polarities are an absolute nightmare, as
+        * we need to evaluate the bit in the light of the feature
+        * that defines it. WTF were they thinking?
+        *
+        * So let's check if the bit has been earmarked as RES0, as
+        * this indicates an unimplemented feature.
+        */
+       if (val & BIT(tc.bit))
+               return false;
+
+       switch ((enum fgt_group_id)tc.fgt) {
+       case HFGxTR_GROUP:
+               sr = is_read ? HFGRTR_EL2 : HFGWTR_EL2;
+               break;
+
+       case HDFGRTR_GROUP:
+               sr = is_read ? HDFGRTR_EL2 : HDFGWTR_EL2;
+               break;
+
+       case HAFGRTR_GROUP:
+               sr = HAFGRTR_EL2;
+               break;
+
+       case HFGITR_GROUP:
+               sr = HFGITR_EL2;
+               break;
+
+       default:
+               WARN_ONCE(1, "Unhandled FGT group");
+               return false;
+       }
+
+       return !(kvm_get_sysreg_res0(kvm, sr) & BIT(tc.bit));
 }
 
 bool __check_nv_sr_forward(struct kvm_vcpu *vcpu)
@@ -1969,7 +2021,8 @@ bool __check_nv_sr_forward(struct kvm_vcpu *vcpu)
                return false;
        }
 
-       if (tc.fgt != __NO_FGT_GROUP__ && check_fgt_bit(val, tc))
+       if (tc.fgt != __NO_FGT_GROUP__ && check_fgt_bit(vcpu->kvm, is_read,
+                                                       val, tc))
                goto inject;
 
        b = compute_trap_behaviour(vcpu, tc);