drm/i915: Extract HAS_DOUBLE_BUFFERED_M_N()
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 7 Sep 2022 09:10:43 +0000 (12:10 +0300)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 7 Sep 2022 18:12:32 +0000 (21:12 +0300)
We have a couple of places that want to make distinction between
double buffered M/N registers vs. the split M1/N1+M2/N2 registers.
Add a helper for that.

v2: Turn into a HAS_ macro (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com> #v1
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220907091057.11572-4-ville.syrjala@linux.intel.com
drivers/gpu/drm/i915/display/intel_display.c
drivers/gpu/drm/i915/display/intel_dp.c
drivers/gpu/drm/i915/i915_drv.h

index 106c594dad3128165d32b472b440bd4e8aa2400b..807a20626a79264ca1958e55483f2589bacaef6c 100644 (file)
@@ -5771,7 +5771,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
        PIPE_CONF_CHECK_I(lane_count);
        PIPE_CONF_CHECK_X(lane_lat_optim_mask);
 
-       if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) {
+       if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
                PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
        } else {
                PIPE_CONF_CHECK_M_N(dp_m_n);
index f52a5f037c3d2e05d397dabbf809779475fb9e3f..a8f0e2dbd8bf7c666e8ddaf3920800afa53bff69 100644 (file)
@@ -1864,8 +1864,7 @@ intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
 static bool cpu_transcoder_has_drrs(struct drm_i915_private *i915,
                                    enum transcoder cpu_transcoder)
 {
-       /* M1/N1 is double buffered */
-       if (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
+       if (HAS_DOUBLE_BUFFERED_M_N(i915))
                return true;
 
        return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder);
index cc45eb759ba7aaa95a269f75f7558a90f0812de3..717c702d2aaf5817bbde9f2a7db111f470c9301c 100644 (file)
@@ -868,6 +868,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_DP_MST(dev_priv)   (INTEL_INFO(dev_priv)->display.has_dp_mst)
 #define HAS_DP20(dev_priv)     (IS_DG2(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
 
+#define HAS_DOUBLE_BUFFERED_M_N(dev_priv)      (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
+
 #define HAS_CDCLK_CRAWL(dev_priv)       (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
 #define HAS_DDI(dev_priv)               (INTEL_INFO(dev_priv)->display.has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)