drm/i915/rkl: Limit number of universal planes to 5

RKL only has five universal planes, plus a cursor.  Since the
bottom-most universal plane is considered the primary plane, set the
number of sprites available on this platform to 4.

In general, the plane capabilities of the remaining planes stay the same
as TGL.  However the NV12 Y-plane support moves down to the new top two
planes and now only the bottom three planes can be used for NV12 UV.

Bspec: 49181
Bspec: 49251
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200504225227.464666-8-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 3da4491bcd2b5e933832c15926fc3c4422f5aaf6..f22d11f127c8509f1b678cff0c3829dca0a0b19e 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12505,7 +12505,7 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
                        continue;
 
                for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
-                       if (!icl_is_nv12_y_plane(linked->id))
+                       if (!icl_is_nv12_y_plane(dev_priv, linked->id))
                                continue;
 
                        if (crtc_state->active_planes & BIT(linked->id))
@@ -12551,6 +12551,10 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
                                plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
                        else if (linked->id == PLANE_SPRITE4)
                                plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
+                       else if (linked->id == PLANE_SPRITE3)
+                               plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL;
+                       else if (linked->id == PLANE_SPRITE2)
+                               plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL;
                        else
                                MISSING_CASE(linked->id);
                }

diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 0000ec7055f74f590e270b6e5ef54455957c4880..571c36f929bda64f2b2788b1e5f4281d08f8a88f 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -333,6 +333,21 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
        return 0;
 }
 
+static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
+{
+       if (IS_ROCKETLAKE(i915))
+               return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
+       else
+               return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
+}
+
+bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
+                        enum plane_id plane_id)
+{
+       return INTEL_GEN(dev_priv) >= 11 &&
+               icl_nv12_y_plane_mask(dev_priv) & BIT(plane_id);
+}
+
 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id)
 {
        return INTEL_GEN(dev_priv) >= 11 &&
@@ -3003,7 +3018,7 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
        if (icl_is_hdr_plane(dev_priv, plane_id)) {
                *num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
                return icl_hdr_plane_formats;
-       } else if (icl_is_nv12_y_plane(plane_id)) {
+       } else if (icl_is_nv12_y_plane(dev_priv, plane_id)) {
                *num_formats = ARRAY_SIZE(icl_sdr_y_plane_formats);
                return icl_sdr_y_plane_formats;
        } else {

diff --git a/drivers/gpu/drm/i915/display/intel_sprite.h b/drivers/gpu/drm/i915/display/intel_sprite.h
index 5eeaa92420d1071d3c41d3ce7568aea70389283c..cd2104ba1ca196ba31377e83851188f320972d1d 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_sprite.h
+++ b/drivers/gpu/drm/i915/display/intel_sprite.h
@@ -32,21 +32,14 @@ struct intel_plane *
 skl_universal_plane_create(struct drm_i915_private *dev_priv,
                           enum pipe pipe, enum plane_id plane_id);
 
-static inline bool icl_is_nv12_y_plane(enum plane_id id)
-{
-       /* Don't need to do a gen check, these planes are only available on gen11 */
-       if (id == PLANE_SPRITE4 || id == PLANE_SPRITE5)
-               return true;
-
-       return false;
-}
-
 static inline u8 icl_hdr_plane_mask(void)
 {
        return BIT(PLANE_PRIMARY) |
                BIT(PLANE_SPRITE0) | BIT(PLANE_SPRITE1);
 }
 
+bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
+                        enum plane_id plane_id);
 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id);
 
 int ivb_plane_min_cdclk(const struct intel_crtc_state *crtc_state,

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4dc601dffc081f8bdba623d96de91f6d1ca19699..95996db46939812033fe052ca47f64a1a41f50e1 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2254,7 +2254,9 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
 
 static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
 {
-       if (INTEL_GEN(dev_priv) >= 11)
+       if (IS_ROCKETLAKE(dev_priv))
+               return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
+       else if (INTEL_GEN(dev_priv) >= 11)
                return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
        else if (INTEL_GEN(dev_priv) >= 9)
                return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f774ec2bcc99818c8116236487884192ac01644a..e9d50fe0f375849d8dcac8e6d37c340f8c559287 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6912,6 +6912,8 @@ enum {
 #define _PLANE_CUS_CTL_1_A                     0x701c8
 #define _PLANE_CUS_CTL_2_A                     0x702c8
 #define  PLANE_CUS_ENABLE                      (1 << 31)
+#define  PLANE_CUS_PLANE_4_RKL                 (0 << 30)
+#define  PLANE_CUS_PLANE_5_RKL                 (1 << 30)
 #define  PLANE_CUS_PLANE_6                     (0 << 30)
 #define  PLANE_CUS_PLANE_7                     (1 << 30)
 #define  PLANE_CUS_HPHASE_SIGN_NEGATIVE                (1 << 19)
@@ -7578,6 +7580,9 @@ enum {
         GEN11_PIPE_PLANE7_FAULT | \
         GEN11_PIPE_PLANE6_FAULT | \
         GEN11_PIPE_PLANE5_FAULT)
+#define RKL_DE_PIPE_IRQ_FAULT_ERRORS \
+       (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
+        GEN11_PIPE_PLANE5_FAULT)
 
 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
 #define GEN8_DE_PORT_IMR _MMIO(0x44444)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index e5e6836f8fa09b7316ce76298e242b23d13e2c18..c245c10c9bee7cb084ee8baafde82111b71a753f 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -934,7 +934,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 
        BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
 
-       if (INTEL_GEN(dev_priv) >= 11)
+       if (IS_ROCKETLAKE(dev_priv))
+               for_each_pipe(dev_priv, pipe)
+                       runtime->num_sprites[pipe] = 4;
+       else if (INTEL_GEN(dev_priv) >= 11)
                for_each_pipe(dev_priv, pipe)
                        runtime->num_sprites[pipe] = 6;
        else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv))