target/sparc: Set FloatInfZeroNaNRule explicitly
authorPeter Maydell <peter.maydell@linaro.org>
Wed, 11 Dec 2024 15:30:55 +0000 (15:30 +0000)
committerPeter Maydell <peter.maydell@linaro.org>
Wed, 11 Dec 2024 15:30:55 +0000 (15:30 +0000)
Set the FloatInfZeroNaNRule explicitly for the SPARC target,
so we can remove the ifdef from pickNaNMulAdd().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241202131347.498124-10-peter.maydell@linaro.org

fpu/softfloat-specialize.c.inc
target/sparc/cpu.c

index db9a466e05b859306e5e1b716a842a49074984e7..7e57e85348bcd383109b302d806f1f53f9379813 100644 (file)
@@ -489,8 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
         /*
          * Temporarily fall back to ifdef ladder
          */
-#if defined(TARGET_SPARC) || \
-    defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
+#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
     defined(TARGET_I386) || defined(TARGET_LOONGARCH)
         /*
          * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
index dd7af86de735d92b218f0f6e4ca301653c1b8c75..61f2d3fbf23a96330f7db4e077d5f3f332d84b1e 100644 (file)
@@ -814,6 +814,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
      * the CPU state struct so it won't get zeroed on reset.
      */
     set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
+    /* For inf * 0 + NaN, return the input NaN */
+    set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
 
     cpu_exec_realizefn(cs, &local_err);
     if (local_err != NULL) {