arm64: dts: mt8195: Add panfrost node for Mali-G57 Valhall Natt GPU

Add GPU support through panfrost for the Mali-G57 GPU on MT8195
with its OPP table but keep it in disabled state.

This is expected to be enabled only on boards which make use of
the GPU.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230301095523.428461-16-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 6767bac3f69e1a1034f46756a45a32def9008fca..b0ee4dc4ce20f9fb6dfe946c00982a27da8edb6f 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -333,6 +333,76 @@
                #performance-domain-cells = <1>;
        };
 
+       gpu_opp_table: opp-table-gpu {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-390000000 {
+                       opp-hz = /bits/ 64 <390000000>;
+                       opp-microvolt = <625000>;
+               };
+               opp-410000000 {
+                       opp-hz = /bits/ 64 <410000000>;
+                       opp-microvolt = <631250>;
+               };
+               opp-431000000 {
+                       opp-hz = /bits/ 64 <431000000>;
+                       opp-microvolt = <631250>;
+               };
+               opp-473000000 {
+                       opp-hz = /bits/ 64 <473000000>;
+                       opp-microvolt = <637500>;
+               };
+               opp-515000000 {
+                       opp-hz = /bits/ 64 <515000000>;
+                       opp-microvolt = <637500>;
+               };
+               opp-556000000 {
+                       opp-hz = /bits/ 64 <556000000>;
+                       opp-microvolt = <643750>;
+               };
+               opp-598000000 {
+                       opp-hz = /bits/ 64 <598000000>;
+                       opp-microvolt = <650000>;
+               };
+               opp-640000000 {
+                       opp-hz = /bits/ 64 <640000000>;
+                       opp-microvolt = <650000>;
+               };
+               opp-670000000 {
+                       opp-hz = /bits/ 64 <670000000>;
+                       opp-microvolt = <662500>;
+               };
+               opp-700000000 {
+                       opp-hz = /bits/ 64 <700000000>;
+                       opp-microvolt = <675000>;
+               };
+               opp-730000000 {
+                       opp-hz = /bits/ 64 <730000000>;
+                       opp-microvolt = <687500>;
+               };
+               opp-760000000 {
+                       opp-hz = /bits/ 64 <760000000>;
+                       opp-microvolt = <700000>;
+               };
+               opp-790000000 {
+                       opp-hz = /bits/ 64 <790000000>;
+                       opp-microvolt = <712500>;
+               };
+               opp-820000000 {
+                       opp-hz = /bits/ 64 <820000000>;
+                       opp-microvolt = <725000>;
+               };
+               opp-850000000 {
+                       opp-hz = /bits/ 64 <850000000>;
+                       opp-microvolt = <737500>;
+               };
+               opp-880000000 {
+                       opp-hz = /bits/ 64 <880000000>;
+                       opp-microvolt = <750000>;
+               };
+       };
+
        pmu-a55 {
                compatible = "arm,cortex-a55-pmu";
                interrupt-parent = <&gic>;
@@ -1790,6 +1860,26 @@
                        status = "disabled";
                };
 
+               gpu: gpu@13000000 {
+                       compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali",
+                                    "arm,mali-valhall-jm";
+                       reg = <0 0x13000000 0 0x4000>;
+
+                       clocks = <&mfgcfg CLK_MFG_BG3D>;
+                       interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>,
+                                    <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>,
+                                    <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>;
+                       interrupt-names = "job", "mmu", "gpu";
+                       operating-points-v2 = <&gpu_opp_table>;
+                       power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>,
+                                       <&spm MT8195_POWER_DOMAIN_MFG3>,
+                                       <&spm MT8195_POWER_DOMAIN_MFG4>,
+                                       <&spm MT8195_POWER_DOMAIN_MFG5>,
+                                       <&spm MT8195_POWER_DOMAIN_MFG6>;
+                       power-domain-names = "core0", "core1", "core2", "core3", "core4";
+                       status = "disabled";
+               };
+
                mfgcfg: clock-controller@13fbf000 {
                        compatible = "mediatek,mt8195-mfgcfg";
                        reg = <0 0x13fbf000 0 0x1000>;