riscv: errata: Make ERRATA_STARFIVE_JH7100 depend on !DMA_DIRECT_REMAP
authorEmil Renner Berthing <emil.renner.berthing@canonical.com>
Fri, 15 Dec 2023 19:09:09 +0000 (20:09 +0100)
committerConor Dooley <conor.dooley@microchip.com>
Sat, 16 Dec 2023 23:37:38 +0000 (23:37 +0000)
Similar to the Renesas RZ/Five[1] the JH7100 SoC needs the non-portable
CONFIG_DMA_GLOBAL_POOL enabled which is incompatible with DMA_DIRECT_REMAP
selected by RISCV_ISA_ZICBOM.

[1]: commit 31b2daea0764 ("soc: renesas: Make RZ/Five depend on !DMA_DIRECT_REMAP")

Link: https://lore.kernel.org/all/24942b4d-d16a-463f-b39a-f9dfcb89d742@infradead.org/
Fixes: 64fc984a8a54 ("riscv: errata: Add StarFive JH7100 errata")
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
arch/riscv/Kconfig.errata

index 692de149141fcd97478c764562684b701b8f039d..f5c432b005e77a46b4cdc1ed3f8b8ae160d2b1a0 100644 (file)
@@ -55,7 +55,9 @@ config ERRATA_SIFIVE_CIP_1200
 
 config ERRATA_STARFIVE_JH7100
        bool "StarFive JH7100 support"
-       depends on ARCH_STARFIVE && NONPORTABLE
+       depends on ARCH_STARFIVE
+       depends on !DMA_DIRECT_REMAP
+       depends on NONPORTABLE
        select DMA_GLOBAL_POOL
        select RISCV_DMA_NONCOHERENT
        select RISCV_NONSTANDARD_CACHE_OPS