riscv: dts: thead: Fix node ordering in TH1520 device tree

According to the device tree coding style, nodes shall be ordered by
unit address in ascending order.

Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 8b915e206f3a01a1f7cfb5a3a78217b3df2e26a0..d2fa25839012c3852867e331cd3c042bf0474ea7 100644 (file)
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -193,6 +193,33 @@
                        status = "disabled";
                };
 
+               emmc: mmc@ffe7080000 {
+                       compatible = "thead,th1520-dwcmshc";
+                       reg = <0xff 0xe7080000 0x0 0x10000>;
+                       interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&sdhci_clk>;
+                       clock-names = "core";
+                       status = "disabled";
+               };
+
+               sdio0: mmc@ffe7090000 {
+                       compatible = "thead,th1520-dwcmshc";
+                       reg = <0xff 0xe7090000 0x0 0x10000>;
+                       interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&sdhci_clk>;
+                       clock-names = "core";
+                       status = "disabled";
+               };
+
+               sdio1: mmc@ffe70a0000 {
+                       compatible = "thead,th1520-dwcmshc";
+                       reg = <0xff 0xe70a0000 0x0 0x10000>;
+                       interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&sdhci_clk>;
+                       clock-names = "core";
+                       status = "disabled";
+               };
+
                uart1: serial@ffe7f00000 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0xff 0xe7f00000 0x0 0x100>;
@@ -311,33 +338,6 @@
                        status = "disabled";
                };
 
-               emmc: mmc@ffe7080000 {
-                       compatible = "thead,th1520-dwcmshc";
-                       reg = <0xff 0xe7080000 0x0 0x10000>;
-                       interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&sdhci_clk>;
-                       clock-names = "core";
-                       status = "disabled";
-               };
-
-               sdio0: mmc@ffe7090000 {
-                       compatible = "thead,th1520-dwcmshc";
-                       reg = <0xff 0xe7090000 0x0 0x10000>;
-                       interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&sdhci_clk>;
-                       clock-names = "core";
-                       status = "disabled";
-               };
-
-               sdio1: mmc@ffe70a0000 {
-                       compatible = "thead,th1520-dwcmshc";
-                       reg = <0xff 0xe70a0000 0x0 0x10000>;
-                       interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&sdhci_clk>;
-                       clock-names = "core";
-                       status = "disabled";
-               };
-
                timer0: timer@ffefc32000 {
                        compatible = "snps,dw-apb-timer";
                        reg = <0xff 0xefc32000 0x0 0x14>;